DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 objected to because of the following informalities:
An error determining system, comprising a processor and a non-transitory memory, the processor, wherein the non-transitory memory comprises a plurality of medium particles that are configured to generate error information…
The claim recites subject “the processor”, but fails to recite any further limitations or structural relationships regarding this subject. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 10-12, 16-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ilic (US 11734103 B2).
Regarding Claim 1, Ilic teaches:
An error determining method performed by a processor in an error determining system, (Ilic, Fig. 1, 110, Col. 3, line 42-44, The time series data thus provides a signal that can be analyzed by a supervisory node to identify the behavior of an associated die. Col. 8, line 4-8, Supervisory node 531 may be implemented on suitable computing device having an architecture the same as or similar to that of computing device 901 in FIG. 9. Examiner's note: Computer device 901 includes a processing system 908, also, analyzing data requires processing)
the method comprising: obtaining, by the processor, error information that indicates a medium particle in which an error occurs in a plurality of medium particles of the error determining system; (Ilic, Col. 5, line 51-56, In operation, the supervisory node collects telemetry data from one or more drives (step 301). The telemetry data includes, for example, times series data indicative of the accumulation of bad blocks on one or more dies over time. The supervisory node then processes the data to identify one or more behaviors of one or more of the dies (step 303).)
and determining, by the processor based on the error information, the medium particle in which the error occurs. (Ilic, Col. 6, line 8-10, Regardless of how the behavior of a given die is determined, the supervisory node next determines to retire a given die based on its identified behavior (step 305))
Regarding Claim 2, Ilic teaches:
The method according to claim 1, wherein the error determining system further comprises a control interface circuit coupled to the processor through a line; (Ilic, Fig. 1, 101, Col. 4, line 14-18, Operational environment 100 includes controller 101 and supervisory node 110. Controller 101 interfaces with supervisory node 110 to manage one or more of a set of dies represented by die 103, die 105, and die 107.)
and wherein the obtaining, by the processor, the error information comprises: receiving, by the processor through the line, the error information sent by the control interface circuit. (Ilic, Fig. 1, 101->110, Col. 5, line 19-20, The controller then communicates the telemetry data to a supervisory node (step 203).)
Regarding Claim 10, Ilic teaches:
The method according to claim 1, wherein the error information comprises an identifier of the medium particle in which the error occurs. (Ilic, Col. 5, line 52-54, the telemetry data includes, for example, times series data indicative of the accumulation of bad blocks on one or more dies over time. )
Regarding Claim 11, Ilic teaches:
An error determining system, comprising a processor (Ilic, Fig. 5A, 531) and a non-transitory memory (Ilic, Fig. 5A, 501), the processor,
wherein the non-transitory memory comprises a plurality of medium particles that are configured to generate error information, (Ilic, Col. 8, line 12-15, flash devices 511, 512, 513, 514, 515, 516, 517, and 518 each include a set of dies represented by die groups 521, 522, 523, 524, 525, 526, 527, and 528 respectively. Col. 5, line 4-18, To begin, the controller generates or otherwise obtains telemetry data indicative of one or more operational metrics of the drive (step 201). The telemetry data may include, for example, time series data descriptive of the number of bad blocks recorded periodically with respect to one or more of the dies on the drive. The telemetry data may also include: a total number of uncorrectable errors per read grown defect (bad block); read recovery statistics (counters of read recovery levels per physical die); program erase cycles per SSD-type redundant array of inexpensive disks (referred herein to as RAID) block; a list of grown defects (identified by RAID block, physical and/or logical unit number, channel, and reason—read, program, erase); and total accumulated uncorrectable read errors and program erase cycles per-block.)
wherein the error information indicates a medium particle in which an error occurs in the plurality of medium particles; (Ilic, Col. 5, line 52-56, the telemetry data includes, for example, times series data indicative of the accumulation of bad blocks on one or more dies over time. The supervisory node then processes the data to identify one or more behaviors of one or more of the dies (step 303).)
and the processor is configured to: obtain the error information; (Ilic, Col. 5, line 51-52, In operation, the supervisory node collects telemetry data from one or more drives (step 301). )
and determine, based on the error information, the medium particle in which the error occurs. (Ilic, Col. 6, line 8-10, Regardless of how the behavior of a given die is determined, the supervisory node next determines to retire a given die based on its identified behavior (step 305))
Regarding Claim 12,
The system of claim 12 performs the same method steps as the method of claim 2, and claim 12 is therefore rejected using the same rationale set forth above in the rejection of claim 2
Regarding Claim 16,
The system of claim 16 performs the same method steps as the method of claim 10, and claim 16 is therefore rejected using the same rationale set forth above in the rejection of claim 10
Regarding Claim 17,
The system of claim 17 performs the same method steps as the method of claim 2, and claim 17 is therefore rejected using the same rationale set forth above in the rejection of claim 2
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ilic (US 11734103 B2), in view of HU (US 20160055052 A1)
Regarding Claim 4, Ilic teaches:
and the line comprises a first bus. (Ilic, Fig. 5A, 530, Col. 8, line 3-4, Examples of connection 530 include SAS, SATA, PCIe, and Ethernet connections.)
Ilic does not explicitly teach:
The method according to claim 2, wherein the processor comprises a processing core,
the control interface circuit comprises a registering clock driver (RCD),
However, HU teaches:
The method according to claim 2, wherein the processor comprises a processing core, (Hu, [0050] For example, the processor 104 may be a general purpose processor, a digital signal processor (DSP), a graphics processing unit (GPU), an application specific integrated circuit, a programmable logic device, or the like. Examiner's note: a GPU always has cores)
the control interface circuit comprises a registering clock driver (RCD), (HU, Fig. 12, 1228, [0086] FIG. 12 is a schematic view of a system with a memory system architecture with a correctible error module and a serial presence detect/registering clock driver module sharing an interface according to an embodiment.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Ilic with GPU and RCD as taught by HU, because the processor 104 may be any device configured to be operatively coupled to the memory 102 and capable of executing instructions. (HU, [0050]), and the SPD/RCD module 1228 is configured to access information related to a serial presence detect system and/or a registering clock driver system. (HU, [0087])
Regarding Claim 14,
The system of claim 14 performs the same method steps as the method of claim 4, and claim 14 is therefore rejected using the same rationale set forth above in the rejection of claim 4
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ilic (US 11734103 B2), in view of Lambert (US 20210081286 A1)
Regarding Claim 5, Ilic does not explicitly teach:
The method according to claim 2, wherein the processor comprises a processing core,
the control interface circuit comprises a complex programmable logic device (CPLD),
and the line comprises a second bus.
However, Lambert teaches:
The method according to claim 2, wherein the processor comprises a processing core, (Lambert, Fig. 4, 110. Examiner's note: a CPU always has cores)
the control interface circuit comprises a complex programmable logic device (CPLD), (Lambert, Fig. 4, 140)
and the line comprises a second bus. (Lambert, Fig. 4, 470 and 472+160, [0022] Here, information handling system 100 is illustrated as including a data connection 470 between CPU 110 and CPLD 140, and an I2C sense connection 472 to sense transactions on I2C bus 160.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Ilic with CPU, CPLD and second bus as taught by Lambert, so when CPU 110 issues a command to enable or disable the voltage regulator on a DIMM, CPLD 140 snoops the transaction associated with the command on I2C bus 160 via sense connection 472... (Lambert, [0023])
Allowable Subject Matter
Claims 3, 6-9, 13, 15, 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ilic (US 11734103 B2): Systems, methods, and software are disclosed herein that enhance the management of storage sub-systems with solid-state media. In various implementations, a method comprises collecting time series data indicative of an accumulation of bad blocks within dies on one or more solid-state drives. For one or more of the dies, the method includes identifying one or more behaviors of a die based at least on a portion of the time series data associated with the die and determining to retire the die based at least on one or more identified behaviors of the die. One or more of the dies on the one or more solid-state drives may then be retired accordingly.
HU (US 20160055052 A1): An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.
Lambert (US 20210081286 A1): An information handling system includes a memory device having a voltage regulator enabled by a command from a processor. The memory device provides an indication to a logic device that the voltage regulator successfully powered up the memory device. A failure to provide the indication within a time duration indicates that the voltage regulator failed to successfully power up the memory device. The logic device determines that the processor issued the first command, sends a second indication to the processor indicating that the first voltage regulator successfully powered up the first memory device when the first indication is received within the first time duration after determining that the processor issued the first command, and sends a third indication to the processor that the first voltage regulator failed to successfully power up the first memory device when the first indication is not received within the first time duration after determining that the processor issued the first command.
Vyas (US 11922025 B2): A method includes determining that a criteria involving a memory device is met and performing a defect scan involving memory dice of the memory device in response to the criteria being met. The method further includes determining, as part of performing the defect scan, whether at least one memory die of the memory device has experienced degradation. The defect scan is performed as part of a quality and reliability assurance test or a reliability demonstration test, or both.
SUN (US 20240394160 A1): A hot storage backup system and method for server, relating to the technical field of servers. The method includes: after a Complex Programming Logic Device (CPLD) in a hard disk backboard detects access of a hard disk, triggering a hard disk access signal and sending same to a Central Processing Unit (CPU), and sending command parameters, corresponding to the hard disk, combined by a Basic Input Output System (BIOS) to the CPU; and checking, by the CPU, the command parameters with a mapping table, and in the case that the check is successful, setting an Advanced Configuration and Power Management Interface (ACPI) protocol according to the command parameters, so that the server normally recognizes the hard disk, thereby implementing a hot storage backup function through the hard disk.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XINYUAN YU whose telephone number is (571)272-7140. The examiner can normally be reached Monday-Friday 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XINYUAN YU/Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113