DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application discloses and claims only subject matter disclosed in prior Application No. 18017671, filed 1/24/2023, and names the inventor or at least one joint inventor named in the prior application. Accordingly, this application may constitute a continuation or divisional. Should applicant desire to claim the benefit of the filing date of the prior application, attention is directed to 35 U.S.C. 120, 37 CFR 1.78, and MPEP § 211 et seq. The presentation of a benefit claim may result in an additional fee under 37 CFR 1.17(w)(1) or (2) being required, if the earliest filing date for which benefit is claimed under 35 U.S.C. 120, 121, 365(c), or 386(c) and 1.78(d) in the application is more than six years before the actual filing date of the application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12210255. Although the claims at issue are not identical, they are not patentably distinct from each other because both applications recite substantially similar claim limitations.
19/013073
U.S. Patent No. 12210255
claim 1, An array substrate, comprising a base substrate, a signal line and a plurality of first pixel units; wherein
the signal line is disposed on a bearing surface of the base substrate, and comprises a gate line, a data line, and a discharge line, wherein the gate line extends along a first direction, the data line extends along a second direction, the discharge line extends along a third direction, both the second direction and the third direction are intersected with the first direction; and
each of the plurality of first pixel units comprises a first pixel electrode, a first thin film transistor, a second thin film transistor, and a first connection line; wherein orthographic projections of the first thin film transistor and the second thin film transistor on the bearing surface are both at least partially overlapped with an orthographic projection of the gate line on the bearing surface; and
a control electrode of the first thin film transistor and a control electrode of the second thin film transistor are both electrically connected to the gate line, a first electrode of the first thin film transistor is electrically connected to the data line, a second electrode of the first thin film transistor and a first electrode of the second thin film transistor are both electrically connected to the first pixel electrode by the first connection line, and a second electrode of the second thin film transistor is electrically connected to the discharge line,
wherein the first pixel unit further comprises a first storage capacitor electrode plate, the first storage capacitor electrode plate and the first pixel electrode form a first storage capacitor, and wherein the first storage capacitor electrode plate comprises a first extension portion, a second extension portion, a third extension portion, a fourth extension portion, a fifth extension portion, a sixth extension portion, and a seventh extension portion sequentially connected, the first extension portion, the fourth extension portion and the seventh extension portion extend along the first direction, the second extension portion, the third extension portion, the fifth extension portion and the sixth extension portion extend along the second direction, the second extension portion and the sixth extension portion are arranged opposite each other along the first direction, the third extension portion and the fifth extension portion are arranged opposite each other along the first direction, a first gap exists between the first extension portion and the seventh extension portion, an orthographic projection of the discharge line on the bearing surface is partially within an orthographic projection of the first gap on the bearing surface, and is not overlapped with an orthographic projection of the first extension portion on the bearing surface and is not overlapped with an orthographic projection of the seventh extension portion on the bearing surface.
1. An array substrate, comprising a base substrate, a signal line and a plurality of first pixel units; wherein
the signal line is disposed on a bearing surface of the base substrate, and comprises a gate line, a data line, and a discharge line that are insulated from each other, wherein the gate line extends along a first direction, the data line extends along a second direction, the discharge line extends along a third direction, both the second direction and the third direction being intersected with the first direction, and the gate line and the data line are intersected with each other to define a plurality of sub-pixel regions; and
the first pixel unit comprises a first pixel electrode, a first thin film transistor, a second thin film transistor, and a first connection line; wherein
a plurality of the first pixel electrodes are respectively disposed in the plurality of sub-pixel regions, and orthographic projections of the first thin film transistor and the second thin film transistor on the bearing surface are both at least partially overlapped with an orthographic projection of the gate line on the bearing surface; and
a control electrode of the first thin film transistor and a control electrode of the second thin film transistor are both electrically connected to the gate line, a first electrode of the first thin film transistor is electrically connected to the data line, a second electrode of the first thin film transistor and a first electrode of the second thin film transistor are both electrically connected to the discharge line by the first connection line, and a second electrode of the second thin film transistor is electrically connected to the discharge line,
wherein the first pixel electrode comprises a first part and a second part that are connected to each other, wherein the first part and the second part are arranged along the second direction, the first part and the second part are misaligned with each other in the first direction, and an orthographic projection of the data line on the bearing surface is not overlapped with an orthographic projection of the first part on the bearing surface and an orthographic projection of the second part on the bearing surface, and
wherein the first pixel unit further comprises a first storage capacitor electrode plate, the first storage capacitor electrode plate and the first pixel electrode form a first storage capacitor, and wherein the first storage capacitor electrode plate comprises a first extension portion, a second extension portion, a third extension portion, a fourth extension portion, a fifth extension portion, a sixth extension portion, and a seventh extension portion sequentially connected, the first extension portion, the fourth extension portion and the seventh extension portion extend along the first direction, the second extension portion, the third extension portion, the fifth extension portion and the sixth extension portion extend along the second direction, the second extension portion and the sixth extension portion are arranged opposite each other along the first direction, the third extension portion and the fifth extension portion are arranged opposite each other along the first direction, a width of either the second extension portion or the fifth extension portion along the first direction is greater than a width of the third extension portion along the first direction and is greater than a width of the sixth extension portion along the first direction, the orthographic projection of the first part on the bearing surface is partially overlapped with orthographic projections of the second extension portion and the sixth extension portion on the bearing surface, the orthographic projection of the second part on the bearing surface is partially overlapped with orthographic projections of the third extension portion and the fifth extension portion on the bearing surface; a gap exists between the first extension portion and the seventh extension portion, an orthographic projection of the discharge line on the bearing surface is partially within an orthographic projection of the gap on the bearing surface, and is not overlapped with an orthographic projection of the first extension portion on the bearing surface and is not overlapped with an orthographic projection of the seventh extension portion on the bearing surface.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1, 19, 20 are objected to because of the following informalities:
Claim 1 recites “each of the plurality of first pixel units comprises a first pixel electrode, a first thin film transistor, a second thin film transistor, and a first connection line; wherein orthographic projections of the first thin film transistor and the second thin film transistor on the bearing surface are both at least partially overlapped with an orthographic projection of the gate line on the bearing surface;”.
Claim 1 recites “wherein the first pixel unit further comprises a first storage capacitor electrode plate, the first storage capacitor electrode plate and the first pixel electrode form a first storage capacitor, and wherein the first storage capacitor electrode plate comprises a first extension portion, a second extension portion, a third extension portion, a fourth extension portion, a fifth extension portion, a sixth extension portion, and a seventh extension portion sequentially connected, the first extension portion, the fourth extension portion and the seventh extension portion extend along the first direction, the second extension portion, the third extension portion, the fifth extension portion and the sixth extension portion extend along the second direction, the second extension portion and the sixth extension portion are arranged opposite each other along the first direction, the third extension portion and the fifth extension portion are arranged opposite each other along the first direction, a first gap exists between the first extension portion and the seventh extension portion, an orthographic projection of the discharge line on the bearing surface is partially within an orthographic projection of the first gap on the bearing surface, and is not overlapped with an orthographic projection of the first extension portion on the bearing surface and is not overlapped with an orthographic projection of the seventh extension portion on the bearing surface.”
The limitation is very long.
Examiner suggests to break this limitation into different limitations to improve claim clarity for claim interpretation.
Claims 19, 20 have same issue as claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
There are many 112(b) issues in claim 1.
As some of example, claim 1 recites “a first direction”, “a second direction” and “a third direction”.
It is unclear the differences between “a first direction”, “a second direction” and “a third direction”.
Are they referring to same direction or different direction or overlapping to each other?
Therefore, claim boundary is indefinite.
Claim 1 recites “….electrically connected to ,,,,,”, “electrically connected to …..by the first connected line”.
Claim is unclear whether connections are physically directly connected by …. the ,,, line” or “electrically indirectly connected by an uninterrupted, conductive pathway that allows electrical current to flow between two or more points”.
Claim 1 recites “the first pixel unit” in line 18.
Claim 1 recites “a plurality of first pixel units” in line 1.
Claim 1 is unclear “the first pixel unit” in line 18 refer to which pixel unit.
Claim 1 recites “the first pixel electrode” in line 19.
Claim 1 recites “each of the plurality of first pixel units comprises a first pixel electrode” in line 7.
Claim is unclear “the first pixel electrode” in line 19 belong to which pixel unit.
Examiner suggests applicant review all claims and correct any deficiencies.
Claims 19, 20 have same issue as claim 1.
Claims 2 – 18 have same issue because of claim dependency.
Allowable Subject Matter
Claims 1, 19, 20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) and double patenting rejection, set forth in this Office action.
Claims 2 - 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) and double patenting rejection, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 1, 19, 20:
The closest prior art is Park et al. (U.S. Patent Publication 2021/0278734 A1).
However, the prior art does not teach or suggest either singularly or in combination the specifically claimed, “wherein the first pixel unit further comprises a first storage capacitor electrode plate, the first storage capacitor electrode plate and the first pixel electrode form a first storage capacitor, and wherein the first storage capacitor electrode plate comprises a first extension portion, a second extension portion, a third extension portion, a fourth extension portion, a fifth extension portion, a sixth extension portion, and a seventh extension portion sequentially connected, the first extension portion, the fourth extension portion and the seventh extension portion extend along the first direction, the second extension portion, the third extension portion, the fifth extension portion and the sixth extension portion extend along the second direction, the second extension portion and the sixth extension portion are arranged opposite each other along the first direction, the third extension portion and the fifth extension portion are arranged opposite each other along the first direction, a first gap exists between the first extension portion and the seventh extension portion, an orthographic projection of the discharge line on the bearing surface is partially within an orthographic projection of the first gap on the bearing surface, and is not overlapped with an orthographic projection of the first extension portion on the bearing surface and is not overlapped with an orthographic projection of the seventh extension portion on the bearing surface.”, in the context of the rest of the claimed limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20160291383 A1 discloses thin film transistor arrange in second direction on Figs. 3. 6.
US 20120274884 A1 discloses array substrate on Figs, 7, 9.
US 20220308407 A1 discloses array substrate on Fig. 6.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN-NAN LIN whose telephone number is (571)272-5646. The examiner can normally be reached Monday - Thursday 7:30am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at 571-2722963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN-NAN LIN/Primary Examiner, Art Unit 2629
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