Detailed Action
summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on January 08, 2025.
2. Claims 1-20 are pending and have been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d), which the certified copy has been placed in the record of the file.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 01/08/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. Drawings submitted on 01/08/2025 are acceptable.
Specification
6. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recite “a peak value” in line 3. There is insufficient antecedent basis for this limitation.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4-8 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Kishioka “JP 2013198253”
In regard to claim 1, Kishioka disclose a direct current DC-DC converter (Figs. 1-3: DC/DC converter) comprising: a voltage conversion circuit that includes an inductor and an output capacitor (switch 3, switch 4, inductor L and Cout are equivalent to voltage conversion ) and converts an input voltage (Vin) and to produce an output voltage (Vout) ; a current detection circuit ( Electric current detector 14 ) that detects an inductor current and generates a sensing current during an on-time (the sensed current by detector 14, see page 4, lines 16-17) , energizing the inductor current flowing through the inductor (L) ;
a pulse skip reference voltage generation circuit (a combination of Slope circuit 9 and Pulse skip reference voltage formation circuit 10) that generates a sensing voltage (current source 92 forms specified fixed electric current from sense voltage V14 and generates signal S9 see page 5, lines 10-12) and a pulse skip reference voltage using the sensing current ( pulse skip reference voltage V10. The pulse skip reference voltage formation circuit 10 is configured to receive an output setting voltage detection signal S24 which is caused by voltage V16 for specified detection, through node LX. Examiner noted that voltage detection signal V16 is detected from node LX of the inductor so as the electric current detector 14, thus pulse skip reference voltage V16/S24 and V14/S9 are based on the current sensed from the same node LX of the inductor); and
a control circuit (Figs. 1-3: excluding switch 3, switch 4, inductor L and Cout are equivalent control circuit ) that determines whether to skip a pulse of the voltage conversion circuit and controls the on-time (switching control circuit 1 control the on time switches S3 and S4 based on control signals S6-S7 and S14) , using the sensing voltage (V14/S9) , the pulse skip reference voltage (V10) , and a feedback voltage proportional (feedback voltage 50) to the output voltage (Vout), wherein the pulse skip reference voltage generation circuit generates the pulse skip reference voltage (V10) by sampling the sensing voltage during a reference on-time (V14/S9).
In regard to claim 4, Kishioka disclose wherein the control circuit (Figs. 1-3: excluding switch 3, switch 4, inductor L and Cout are equivalent control circuit ) includes an error amplifier (Error amplifier 5) that compares the feedback voltage (Vf output from 50) with a reference voltage (12) and outputs an error amplification voltage ( error voltage V8 is from Error amplifier 5) , and determines whether to skip the pulse of the voltage conversion circuit using the pulse skip reference voltage and the error amplification voltage ( skip comparator 7 compare error voltage V8 with Skipped reference V10 to generate pulse skip detection signal S7) .
In regard to claim 5, Kishioka disclose (Figs. 1-3) wherein the voltage conversion circuit skips pulses for a time when a level of the pulse skip reference voltage is equal to or higher than a level of the error amplification voltage (skip comparator 7 compare error voltage V8 with Skipped reference V10 to generate pulse skip detection signal S7. Examiner noted that Skipped reference V10 may be equal to or higher than a level V8 or vise vera based upon a design needs / intended purpose for specific reason or goal for acquiring a desired outcome . Therefore, any skilled person designing the circuit of “Kishioka Figs. 1-3” would have to perform a routine experiment, thereby arriving to the subject matter of claim 5. ) .
In regard to claim 6, Kishioka disclose (Figs. 1-3), wherein the pulse skip involves skipping at least one on-time by the voltage conversion circuit (skip comparator 7 compare error voltage V8 with Skipped reference V10 to generate pulse skip detection signal S7 which shows the relative result in the one pulse forming network is output 14 and the switching control circuit 1 to drive switches 3-4) .
In regard to claim 7, Kishioka disclose (Figs. 1-3), wherein the control circuit includes an error amplifier (Error amplifier 5) that compares the feedback voltage (VF) with a reference voltage (Vref/12) and outputs an error amplification voltage (error voltage V8), and the control circuit controls the on-time (switching control circuit 1 control the on time switches S3 and S4 based on control signals S6-S7 and S14) using the sensing voltage (the voltage detection V16 from node LX generated voltage detection signal S24) and the error amplification voltage ( V8) .
In regard to claim 8, Kishioka disclose (Figs. 1-3), wherein when a point at which a level of the sensing voltage exceeds a level of the error amplification voltage occurs within the reference on-time, the on-time is equal to the reference on-time (skip comparator 4 compare V10 and V8 to determine one pulse signal S14 which possesses specified pulse width, outputs to the switching control circuit 1. )
Claims 1 and 4-8 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Chin “20100301822” .
In regard to claim 1, Chin disclose a direct current DC-DC converter (Figs. 6-9: DC/DC converter) comprising: a voltage conversion circuit that includes an inductor and an output capacitor (Fig. 7 : buck converter ) and converts an input voltage (Vin) and to produce an output voltage (Vout) ; a current detection circuit (Fig.7: phase/current is detected between switch node and inductor) that detects an inductor current and generates a sensing current during an on-time (the sensed current/phase,) , energizing the inductor current flowing through the inductor (L) ;
a pulse skip reference voltage generation circuit (a combination of sawtooth wave generation circuit 252 and average circuit 251) that generates a sensing voltage (signal SAW ) and a pulse skip reference voltage using the sensing current ( PSC_ref); and
a control circuit (a combination pulse skipping circuit 25 and PWM generation circuit 22,) that determines whether to skip a pulse of the voltage conversion circuit and controls the on-time (see prag. 0028 and 0030-0032) , using the sensing voltage (SAW) , the pulse skip reference voltage (PSC_ref);) , and a feedback voltage proportional (FB) to the output voltage (Vref), wherein the pulse skip reference voltage generation circuit generates the pulse skip reference voltage (PSC_Ref) by sampling the sensing voltage during a reference on-time (see prag. 0028 and 0030-0032) .
In regard to claim 4, Chin disclose disclose (Figs.6-9) wherein the control circuit (25 and 22 ) includes an error amplifier (221) that compares the feedback voltage (Vf output from output voltage) with a reference voltage (Vref) and outputs an error amplification voltage ( COM) , and determines (selection circuit 27 selects one between the output signal from the PWM generation circuit 22 and the output signal from the pulse skipping circuit 25, parag.0033 ) whether to skip the pulse of the voltage conversion circuit using the pulse skip reference voltage (PSC-Ref) and the error amplification voltage (duty signal Duty ) .
In regard to claim 5, Chin disclose (Figs. 1-3) wherein the voltage conversion circuit skips pulses for a time when a level of the pulse skip reference voltage is equal to or higher than a level of the error amplification voltage (determines (selection circuit 27 selects one between the output signal from the PWM generation circuit 22 and the output signal from the pulse skipping circuit 25, parag.0033 . Examiner noted that Skipped reference may be equal to or higher than a level or vise vera based upon a design needs / intended purpose for specific reason or goal for acquiring a desired outcome . Therefore, any skilled person designing the circuit of “Chin Figs. 1-3” would have to perform a routine experiment, thereby arriving to the subject matter of claim 5. )
In regard to claim 6, Chin disclose (Figs. 1-3), wherein the pulse skip involves skipping at least one on-time by the voltage conversion circuit (selection circuit 27 selects one between the output signal from the PWM generation circuit 22 and the output signal from the pulse skipping circuit 25 to determine PSM On-time , parag.0033 ) .
In regard to claim 7, Chin disclose (Figs. 1-3), wherein the control circuit includes an error amplifier (Error amplifier 221) that compares the feedback voltage (VF) with a reference voltage (Vref) and outputs an error amplification voltage (COM/duty signal), and the control circuit controls the on-time (switching driver circuit 2 control the on time switches Q1 and Q2 based on control PSM on time and Duty signal) using the sensing voltage (SAW) and the error amplification voltage (Duty signal) .
In regard to claim 8,Chin disclose (Figs. 1-3), wherein when a point at which a level of the sensing voltage exceeds a level of the error amplification voltage occurs within the reference on-time, the on-time is equal to the reference on-time (DC signal PSC_Ref is compared with the sawtooth signal SAW in a comparator 253 to generate a pulse width proportional to Vout/Vin. The pulse width is related to the On-time of the switching regulator under the normal loading condition. Thus, the PSM On-time can be generated according to the output of the comparator 253. The comparator 253 can be a general comparator or a hysteresis comparator., see prag. 0031-00-0032)
253 )
Allowable Subject Matter
9. Claims 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is objected because the prior art in the record fails disclose or suggest the DC-DC converter including the limitation of “wherein the sensing voltage has a peak value at an end of the reference on-time, and the pulse skip reference voltage is within a predetermined range of the peak value of the sensing voltage.”
Claim 3 is dependent on claim 2, thus is also objected to because of its dependency.
10. Claims 9-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 9 is allowed because the prior art in the record fails disclose or suggest the DC-DC converter including the limitation of “wherein the pulse skip reference voltage generation circuit includes a first capacitor, a second capacitor, a first switch and a second switch, samples the sensing voltage in the first capacitor during a reference on-time, and generates the pulse skip reference voltage by holding the sampled voltage in the first capacitor and the second capacitor during an off-time when the inductor current flowing in the inductor is de-energized.”
Claim 19 is allowed because the prior art in the record fails disclose or suggest the DC-DC converter including the limitation of “…a pulse skip reference voltage generation circuit that includes a first capacitor and a second capacitor connected in parallel, and a first switch and a second switch connected in series, and generates a sensing voltage and a pulse skip reference voltage using the sensing current and wherein in the pulse skip reference voltage generation circuit, a first end of the first capacitor and a first end of the second capacitor are connected to ground, a second end of the first capacitor is connected to a node between the first switch and the second switch, and a second end of the second capacitor is connected to the second switch, and the sensing voltage is sampled in the first capacitor by maintaining the first switch in an on-state during a reference on-time, the sampled voltage is held in the first capacitor and the second capacitor by maintaining the second switch in an on-state during an off-time when the inductor current is de-energized, and the pulse skip reference voltage is generated, and the voltage conversion circuit skips pulses when the pulse skip reference voltage is greater than the error amplification voltage.”
Claims 10-18 are dependent on claim 9, thus are also allowed to because of their dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen “20240243660” present invention relates to a switching converter and control method thereof, in particular to a switching converter and control method, both of which have pulse skipping mode.
Yun “20230327548” present invention relates a DC-to-DC converter is mainly used in portable electronic devices, which are powered by a battery, such as a mobile phone and a laptop computer. The portable electronic device includes a plurality of sub-circuits, each of which often uses a voltage level higher or lower than a level of a supply voltage supplied from a battery or an external voltage supply device.
Shiwaya “WO2014038684” the present invention relates Non-isolated type switching regulator. Can also be used for a step-down type switching regulator and a current feedback type step-down type switching regulator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
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