DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 8, 10-12 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. 20210374056 herein Malladi in view of Lyakas et al. 20190108100 herein Lyakas.
Per claim 1, Malladi discloses: volatile memory; and a controller configured to: (¶0048; the disclosed systems can feature a device that plugs onto a cache coherent interface (e.g., a CXL/PCIe5 interface) and can implement various cache and memory protocols (e.g., type-2 device based CXL.cache and CXL.memory protocols). Further, in some examples, the device can include a programmable controller or a processor (e.g., a RISC-V processor) that can be configured to present the remote coherent devices as part of the local system, negotiated using a cache coherent protocol (e.g., a CXL.IO protocol); ¶0116; the disclosed systems can include, but not be limited to, a cache controller, a CXL controller, an intelligent memory controller) receive a command to write data to the volatile memory, wherein the command indicates a logical address associated with the data (¶0068; The enhanced capability CXL switch 130 may include one or more circuits (e.g., it may include an FPGA or an ASIC) to (i) route data to different memory types based on workload (ii) virtualize host addresses to device addresses and/or (iii) facilitate RDMA requests between different servers).
Malladi discloses deduplicating a cache but does not specifically disclose: compare the data to one or more duplicate data patterns to identify whether the data matches a duplicate data pattern of the one or more duplicate data patterns; and map, responsive to the data matching the duplicate data pattern, a physical address associated with the duplicate data pattern to the logical address, without writing the data to the volatile memory.
However, Lyakas discloses: compare the data to one or more duplicate data patterns to identify whether the data matches a duplicate data pattern of the one or more duplicate data patterns; (¶0020; Deduplication layer 112 determines if data pattern U is unique. To determine if a deduplication chunk is unique, deduplication layer 112 generates a fingerprint for data pattern U and compares it to the existing fingerprints for known data patterns in deduplication DB 114. As illustrated) and map, responsive to the data matching the duplicate data pattern, a physical address associated with the duplicate data pattern to the logical address, without writing the data to the volatile memory (¶0020; in FIG. 4, when the fingerprint does not match any existing fingerprint, deduplication layer 112 allocates a new disk chunk in disk 106, writes data pattern U to the new disk chunk in disk 106, and maps deduplication chunk 1 of snapshot chunk 202-2 in virtual volume 102 to the new disk chunk with data pattern U. Note deduplication chunk 1′ of snapshot chunk 204-2 in snapshot 110 still points to the old disk chunk having data pattern X. Deduplication layer 112 also adds the new fingerprint to deduplication DB 114 with a reference count of 1, and decrements the reference count of data pattern X being written over. When the fingerprint matches an existing fingerprint, deduplication layer 112 maps deduplication chunk 1 of snapshot chunk 202-2 in virtual volume 102 to an existing disk chunk in disk 106 and increments the reference count for the corresponding data pattern in deduplication DB 114;the examiner notes that without writing the data is merely not creating a new entry).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Malladi and Lyakas COW deduplicated to keep the operation light weight. Lyakas saves space (¶0005).
Per claim 2, Lykas : derive an entry address using the data; and retrieve, from a data structure of a local memory of the controller, an entry associated with the entry address, wherein the entry indicates the duplicate data pattern and the physical address (¶0020; Deduplication layer 112 determines if data pattern U is unique. To determine if a deduplication chunk is unique, deduplication layer 112 generates a fingerprint for data pattern U and compares it to the existing fingerprints for known data patterns in deduplication DB 114. As illustrated).
Per claim 3, Lyakas discloses: wherein the entry further indicates a reference counter indicating a quantity of logical addresses mapped to the physical address, and wherein the controller is further configured to increment the reference counter responsive to the data matching the duplicate data pattern (¶0020; When the fingerprint matches an existing fingerprint, deduplication layer 112 maps deduplication chunk 1 of snapshot chunk 202-2 in virtual volume 102 to an existing disk chunk in disk 106 and increments the reference count for the corresponding data pattern in deduplication DB 114).
Per claim 4, Lyakas discloses: wherein the controller is further configured to: derive an entry address and a data representation using the data; retrieve, from a data structure of a local memory of the controller, an entry associated with the entry address, wherein the entry indicates a stored data representation and the physical address; compare the data representation and the stored data representation to identify whether the data representation matches the stored data representation; and retrieve, responsive to the data representation matching the stored data representation, the duplicate data pattern from the physical address of the volatile memory (¶0020; When the fingerprint matches an existing fingerprint, deduplication layer 112 maps deduplication chunk 1 of snapshot chunk 202-2 in virtual volume 102 to an existing disk chunk in disk 106 and increments the reference count for the corresponding data pattern in deduplication DB 114; the examiner interprets the data representation as a hash/fingerprint).
Per claim 5, Lyakas discloses: wherein the physical address of the volatile memory is associated with a reference counter indicating a quantity of logical addresses mapped to the physical address, and wherein the controller is further configured to increment the reference counter responsive to the data matching the duplicate data pattern (¶0020; Deduplication layer 112 also adds the new fingerprint to deduplication DB 114 with a reference count of 1, and decrements the reference count of data pattern X being written over. When the fingerprint matches an existing fingerprint, deduplication layer 112 maps deduplication chunk 1 of snapshot chunk 202-2 in virtual volume 102 to an existing disk chunk in disk 106 and increments the reference count for the corresponding data pattern in deduplication DB 114).
Per claim 8, Lyakas discloses: wherein the duplicate data pattern is a configured data pattern (¶0020; Deduplication layer 112 determines if data pattern U is unique. To determine if a deduplication chunk is unique, deduplication layer 112 generates a fingerprint for data pattern U and compares it to the existing fingerprints for known data patterns in deduplication DB 114. As illustrated).
Claims 10-12 are the method claims corresponding to the system claims 1, 2, 4 and are rejected under the same reasons set forth in connection with the rejection of claims 1, 2, 4.
Per claim 15, Malladi discloses: volatile memory; and a compute express link (CXL) controller, comprising:a CXL interface; (¶0048; the disclosed systems can feature a device that plugs onto a cache coherent interface (e.g., a CXL/PCIe5 interface) and can implement various cache and memory protocols (e.g., type-2 device based CXL.cache and CXL.memory protocols). Further, in some examples, the device can include a programmable controller or a processor (e.g., a RISC-V processor) that can be configured to present the remote coherent devices as part of the local system, negotiated using a cache coherent protocol (e.g., a CXL.IO protocol); ¶0116; the disclosed systems can include, but not be limited to, a cache controller, a CXL controller, an intelligent memory controller) r and a controller configured to:receive a command to write data to the volatile memory, wherein the command indicates a logical address associated with the data; (¶0068; The enhanced capability CXL switch 130 may include one or more circuits (e.g., it may include an FPGA or an ASIC) to (i) route data to different memory types based on workload (ii) virtualize host addresses to device addresses and/or (iii) facilitate RDMA requests between different servers).
Malladi discloses deduplicating a cache but does not specifically disclose: compare the data to one or more duplicate data patterns to identify whether the data matches a duplicate data pattern of the one or more duplicate data patterns; and map, responsive to the data matching the duplicate data pattern, a physical address associated with the duplicate data pattern to the logical address, without writing the data to the volatile memory.
However, Lyakas discloses: compare the data to one or more duplicate data patterns to identify whether the data matches a duplicate data pattern of the one or more duplicate data patterns; (¶0020; Deduplication layer 112 determines if data pattern U is unique. To determine if a deduplication chunk is unique, deduplication layer 112 generates a fingerprint for data pattern U and compares it to the existing fingerprints for known data patterns in deduplication DB 114. As illustrated) and map, responsive to the data matching the duplicate data pattern, a physical address associated with the duplicate data pattern to the logical address, without writing the data to the volatile memory (¶0020; in FIG. 4, when the fingerprint does not match any existing fingerprint, deduplication layer 112 allocates a new disk chunk in disk 106, writes data pattern U to the new disk chunk in disk 106, and maps deduplication chunk 1 of snapshot chunk 202-2 in virtual volume 102 to the new disk chunk with data pattern U. Note deduplication chunk 1′ of snapshot chunk 204-2 in snapshot 110 still points to the old disk chunk having data pattern X. Deduplication layer 112 also adds the new fingerprint to deduplication DB 114 with a reference count of 1, and decrements the reference count of data pattern X being written over. When the fingerprint matches an existing fingerprint, deduplication layer 112 maps deduplication chunk 1 of snapshot chunk 202-2 in virtual volume 102 to an existing disk chunk in disk 106 and increments the reference count for the corresponding data pattern in deduplication DB 114;the examiner notes that without writing the data is merely not creating a new entry).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Malladi and Lyakas COW deduplicated to keep the operation light weight. Lyakas saves space (¶0005).
Claims 16-18 are the method claims corresponding to the system claims 1-9 and are rejected under the same reasons set forth in connection with the rejection of claims 1-9.
Claim(s) 6-7, 9, 13-14 and 19-20 and is/are rejected under 35 U.S.C. 103 as being unpatentable over Malladi et al. 20210374056 herein Malladi and Lyakas et al. 20190108100 herein Lyakas in view of Scrivano et al. 20230342173 herein Scrivano.
Per claim 6, the combined teachings of Malladi and Lyakas does not specifically disclose using a CAM: receive an additional command to read the data from the volatile memory, wherein the command indicates the logical address associated with the data; obtain the physical address that is mapped to the logical address by a mapping of logical addresses to physical addresses; (fig. 2, ¶0041; at block 202, the processing logic (e.g., the processing logic that generates or represents a VM) can receive, a request to access a file. For example, the processing logic can receive, at block 202, a request to perform a file access operation with respect to the file. The file and its contents can be accessed at a location recorded in an entry of an HTC table 127A, 128) retrieve, from a content-addressable memory of the controller, an entry address associated with the physical address; retrieve, from a data structure of a local memory of the controller, an entry for the entry address, wherein the entry indicates a data pattern representing previously written data to the volatile memory; and return the data pattern in response to the additional command (¶0014; Deduplication schemes that mitigate duplication of data can be based on content addressable storage (CAS) techniques, which involve storing and retrieving data based content instead of location. Both host systems and the VMs running on them can use CAS systems. CASs use unique identifiers (e.g., a hash function of content) to identify particular files. CAS systems can assign a content address, which is a unique identifier (e.g., a hash or checksum) calculated based on content, to each data object (e.g., file) in the system. Accordingly, CAS systems can be used to map a hash of file content to an identifier of the physical location of the file. To access or retrieve the data in a CAS system, applications can use the content addresses to find the desired files.).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Malladi, Lyakas and Scrivano’s CAM storage system which uses unique ID;s to identify particular files. Scrivano’s CAM implementation reduces data duplication (¶0014).
Per claim 7, Scrivano discloses: receive an additional command to read the data from the volatile memory, wherein the command indicates the logical address associated with the data; obtain the physical address that is mapped to the logical address by a mapping of logical addresses to physical addresses; retrieve duplicate data from the physical address of the volatile memory; and return the duplicate data in response to the additional command (¶0014; Deduplication schemes that mitigate duplication of data can be based on content addressable storage (CAS) techniques, which involve storing and retrieving data based content instead of location. Both host systems and the VMs running on them can use CAS systems. CASs use unique identifiers (e.g., a hash function of content) to identify particular files. CAS systems can assign a content address, which is a unique identifier (e.g., a hash or checksum) calculated based on content, to each data object (e.g., file) in the system. fig. 2, ¶0041; at block 202, the processing logic (e.g., the processing logic that generates or represents a VM) can receive, a request to access a file. For example, the processing logic can receive, at block 202, a request to perform a file access operation with respect to the file. The file and its contents can be accessed at a location recorded in an entry of an HTC table 127A, 128).
Per claim 9, Scrivano discloses: wherein the controller includes a content-addressable memory and a local memory, wherein the local memory is configured to include at least one data structure, and wherein the at least one data structure is configured to include the duplicate data pattern (¶0014; Deduplication schemes that mitigate duplication of data can be based on content addressable storage (CAS) techniques, which involve storing and retrieving data based content instead of location. Both host systems and the VMs running on them can use CAS systems. CASs use unique identifiers (e.g., a hash function of content) to identify particular files. CAS systems can assign a content address, which is a unique identifier (e.g., a hash or checksum) calculated based on content, to each data object (e.g., file) in the system. Accordingly, CAS systems can be used to map a hash of file content to an identifier of the physical location of the file. To access or retrieve the data in a CAS system, applications can use the content addresses to find the desired files).
Claims 13-14 are the method claims corresponding to the system claims 6-7 and are rejected under the same reasons set forth in connection with the rejection of claims 6-7.
Claims 19-20 are the method claims corresponding to the system claims 6-7 and are rejected under the same reasons set forth in connection with the rejection of claims 6-7.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jiang discloses: a deduplication reference count of a same data block n which reaches a maximum number limit (e.g., 256). When the reference count reaches the limit, the data block n will be copied as a new one and its hash entry is updated to record an identifier of the newly copied data block. FIG. 10 illustrates this example, where a set of VLBs 1001-1-1 through 1001-1-V (collectively, VLBs 1001-1) are mapped to physical space block 1003-1. A particular data block n in VLB 1001-1-V is copied to a new VLB 1001-2 and corresponding physical space block 1003-2 when its deduplication reference count reaches the limit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim VO can be reached at 5712723642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
Prosecution Insights