DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakano et al. U.S. Patent Publication No. 2017/0359537 (hereinafter Sakano) in view of Onishi et al. U.S. Patent Publication No. 2016/0050381 (hereinafter Onishi).
Consider claim 1, Sakano teaches a detection device comprising (Figure 1): a sensor circuit provided with a first photodiode and a second photodiode in a semiconductor layer (Figure 1, pixel array unit 41. Figures 5-6, 161); and a signal detector configured to acquire a detection value corresponding to a signal output from the sensor circuit (Figure 1, 43, 48, 200 (see also figure 6)), wherein the first photodiode has one end coupled to the signal detector and another end coupled to a reference potential (Figures 5-6, 161-162 and 200), both ends of the second photodiode are electrically connected to the signal detector (Figures 5-6, 161-162 and 200. Figure 1, pixel array 141).
Sakano does not appear to specifically disclose the signal detector is configured to output a difference value between a detection value acquired by the first photodiode and a detection value acquired by the second photodiode.
However, in a related field of endeavor, Onishi teaches an imaging system (abstract) and further teaches the signal detector is configured to output a difference value between a detection value acquired by the first photodiode and a detection value acquired by the second photodiode (Figure 5 and [0069-0070]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a difference value as taught by Onishi in order to improves common mode rejection ratio and power supply rejection ration as suggested in [0069].
Consider claim 2, Sakano and Onishi teaches all the limitations of claim 1. In addition, Sakano teaches wherein the sensor circuit comprises: a first detection electrode and a second detection electrode that are provided on a detection surface side of the semiconductor layer (Figure 5, 161, 162 and 200); and a first power supply electrode and a second power supply electrode, the first photodiode has one end coupled to the first detection electrode and another end coupled to the first power supply electrode (Figure 5, 161, 162, 200 and Vmid), and the second photodiode has one end coupled to the second detection electrode and another end coupled to the second power supply electrode (Figure 5, 161, 162, 200 and Vmid. Figure 1, pixel array 141).
Consider claim 6, Sakano teaches a detection device comprising: a sensor circuit provided with a first photodiode having a first detection electrode and a first power supply electrode with a semiconductor layer therebetween (Figure 5, Vmid, 161-163 and 200); a second detection electrode adjacent to the first detection electrode (Figure 1, pixel array 141 (and thus a plurality of adjacent electrodes)); and a signal detector configured to acquire a detection value corresponding to a signal output from the sensor circuit (Figure 1, 43, 48, 200 (see also figure 6)), wherein one end of the first detection electrode and the first power supply electrode is coupled to the signal detector (Figure 5, 200 and 161) and another end of the first detection electrode and the first power supply electrode is coupled to a reference potential (Figure 5, 162 and Vmid), the second detection electrode is coupled to the signal detector (Figure 5, 200 and 161. Figure 1, pixel array 141).
Sakano does not appear to specifically disclose the signal detector is configured to output a difference value between a detection value acquired by the first detection electrode and a detection value acquired by the second detection electrode.
However, Onishi teaches the signal detector is configured to output a difference value between a detection value acquired by the first detection electrode and a detection value acquired by the second detection electrode (Figure 5 and [0069-0070]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a difference value as taught by Onishi in order to improves common mode rejection ratio and power supply rejection ration as suggested in [0069].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakano and Onishi as applied to claim 1 above, and further in view of Blessinger U.S. Patent Publication No. 2009/0303363 (hereinafter Blessinger).
Consider claim 3, Sakano and Onishi teaches all the limitations of claim 1. In addition, Sakano teaches wherein the sensor circuit comprises: a first detection electrode that is provided on a detection surface side of the semiconductor layer, and coupled to the one end of the first photodiode (Figure 5, 161 and 200); and a second detection electrode that is provided adjacent to the first detection electrode (Figure 1, pixel array 141 (and thus a plurality of adjacent photodiodes)), and coupled to the one end of the second photodiode (Figure 1, pixel array).
Sakano does not appear to specifically disclose a gain ratio of a gain of the first detection circuit to that of the second detection circuit is set to be substantially equal to a reciprocal of an area ratio of an area of the first detection electrode to that of the second detection electrode.
However, in a related field of endeavor, Blessinger teaches an array of pixel circuits (abstract) and further teaches a gain ratio of a gain of the first detection circuit to that of the second detection circuit is set to be substantially equal to a reciprocal of an area ratio of an area of the first detection electrode to that of the second detection electrode ([0011], different size detector and gain is proportional to the responsive area).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to have different size detector areas as taught by Blessinger in [0011] in order to provide an extended dynamic range.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakano and Onishi as applied to claim 1 above, and further in view of Chen U.S. Patent Publication No. 2018/0349666 (hereinafter Chen).
Consider claim 4, Sakano teaches wherein the sensor circuit comprises: a first detection electrode that is provided on a detection surface side of the semiconductor layer, and coupled to the one end of the first photodiode (Figure 5, 161 and 200); and a second detection electrode that is provided adjacent to the first detection electrode, and coupled to the one end of the second photodiode (Figure 5, 161 and 200. Figure 1, pixel array 141 (and thus a plurality of adjacent photodiodes)).
Sakano does not appear to specifically disclose the second detection electrode is provided so as to surround the first detection electrode.
However, in a related field of endeavor, Chen teaches common-mode noise eliminated in the differential amplifier in [0027] and further teaches the second detection electrode is provided so as to surround the first detection electrode (Figure 7 and [0042], reference electrode 713 and sensing electrode 711).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a reference electrode as taught by Chen with the benefit that the reference sensing signal 720 received by the differential amplifier 223 illustrated in FIG. 7 may also contribute to reducing the DC offset component contained in the differential input signal as suggested in [0043].
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Prior arts do not appear to disclose the states of the switches mentioned in claim 5 in combination to others limitations in the claim and any intervening claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-6 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12,236,707.
Claim 1
Claims 1, 3 and 5 of Patent
A detection device comprising: a sensor circuit provided with a first photodiode and a second photodiode in a semiconductor layer;
A detection device comprising: a sensor circuit provided with a first photodiode in a semiconductor layer;
Claim 3: a second detection circuit coupled to one end of the second photodiode
and a signal detector configured to acquire a detection value corresponding to a signal output from the sensor circuit,
and a signal detector configured to acquire a detection value corresponding to a signal output from the sensor circuit,
wherein the first photodiode has one end coupled to the signal detector and another end coupled to a reference potential, both ends of the second photodiode are electrically connected to the signal detector
wherein the signal detector comprises: a first detection circuit coupled to one end of the first photodiode; a first switch circuit configured to apply a power supply potential to another end of the first photodiode;
and a second switch circuit configured to short both ends of the first photodiode, and wherein the signal detector has: a first state in which the first switch circuit is controlled to be on and the second switch circuit is controlled to be off; and a second state in which the first switch circuit is controlled to be off and the second switch circuit is controlled to be on, and is configured to output a difference value between a detection value acquired by the first detection circuit in the first state and a detection value acquired by the first detection circuit in the second state.
and the signal detector is configured to output a difference value between a detection value acquired by the first photodiode and a detection value acquired by the second photodiode.
Claim 5: to output a difference value between a first detection value acquired by the first detection circuit and a second detection value acquired by the second detection circuit.
Claim 3 of Patent includes the limitations of claim 2.
Claim 4 of Patent includes the limitations of claim 3.
Claims 4-5 of Patent include the limitations of claim 4.
Claim 8 of Patent include the limitations of claim 5.
Claim 1 and 5 of Patent include the limitations of claim 6.
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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