DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 09/04/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 12236707 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakano et al. U.S. Patent Publication No. 2017/0359537 (hereinafter Sakano) in view of Madurawe et al. U.S. Patent Publication No. 2016/0307949 (hereinafter Madurawe) and further in view of Onishi et al. U.S. Patent Publication No. 2016/0050381 (hereinafter Onishi).
Consider claim 1, Sakano teaches a detection device comprising (Figure 1): a sensor circuit provided with a first photodiode and a second photodiode in a semiconductor layer (Figure 1, pixel array unit 41 and thus plurality of photodiodes. Figures 5-6, 161); and a signal detector configured to acquire a detection value corresponding to a signal output from the sensor circuit (Figure 1, 43, 48, 200 (see also figure 6)), wherein the first photodiode has one end coupled to the signal detector and another end coupled to a reference potential (Figures 5-6, 161-162 and 200), both ends of the second photodiode are electrically connected to the signal detector (Figures 5-6, 161-162 and 200. Figure 1, pixel array 141), wherein the signal detector comprises: a first detection circuit coupled to one end of the first photodiode (Figure 1 and figure 6, 43, 48 and 200); and a second switch circuit configured to short both ends of the first photodiode (Figure 6, 164), and the signal detector further comprises: a second detection circuit coupled to one end of the second photodiode provided adjacent to the first photodiode (Figure 1 and figure 6, 43, 48 and 200. Figure 1, pixel array 141 and thus two adjacent photodiodes); and a fourth switch circuit configured to short both ends of the second photodiode (Figure 6, 164).
Sakano does not appear to specifically disclose a first switch circuit configured to apply a power supply potential to another end of the first photodiode; a third switch circuit configured to apply the power supply potential to another end of the second photodiode.
However, in a related field of endeavor, Madurawe teaches image sensor pixels with adjustable body bias (abstract) and further teaches a first switch circuit configured to apply a power supply potential to another end of the first photodiode (Figures 3a-b, control circuitry 326 makes the first switch circuit functionality. [0031], adjustable bias control. "Circuit" and “adjustable” imply switch(es). Element 302 is the photodiode); a third switch circuit configured to apply the power supply potential to another end of the second photodiode (Figures 3a-b, control circuitry 326 makes the first switch circuit functionality. [0031], adjustable bias control. "Circuit" and “adjustable” imply switch(es). Element 302 is the photodiode. Figure 1, image sensor array 16. [0030], FIG. 3A shows the circuitry for operation for a single pixel 300 and that in practical use, there may be an M×N array of pixels arranged in M rows and N columns with the pixels of the array accessed using row and column select circuitry).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a switch or circuit for another end of the photodiode as taught by Madurawe with the benefit that having an adjustable signal offers two modes of operation as suggested in [0031].
Sakano does not appear to specifically disclose the signal detector is configured to output a difference value between a detection value acquired by the first photodiode and a detection value acquired by the second photodiode.
However, in a related field of endeavor, Onishi teaches an imaging system (abstract) and further teaches the signal detector is configured to output a difference value between a detection value acquired by the first photodiode and a detection value acquired by the second photodiode (Figure 5 and [0069-0070]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a difference value as taught by Onishi in order to improves common mode rejection ratio and power supply rejection ration as suggested in [0069].
Consider claim 2, Sakano, Madurawe and Onishi teaches all the limitations of claim 1. In addition, Sakano teaches wherein the sensor circuit comprises: a first detection electrode and a second detection electrode that are provided on a detection surface side of the semiconductor layer (Figure 5, 161, 162 and 200); and a first power supply electrode and a second power supply electrode, the first photodiode has one end coupled to the first detection electrode and another end coupled to the first power supply electrode (Figure 5, 161, 162, 200 and Vmid), and the second photodiode has one end coupled to the second detection electrode and another end coupled to the second power supply electrode (Figure 5, 161, 162, 200 and Vmid. Figure 1, pixel array 141).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakano, Madurawe and Onishi as applied to claim 1 above, and further in view of Blessinger U.S. Patent Publication No. 2009/0303363 (hereinafter Blessinger).
Consider claim 3, Sakano, Madurawe and Onishi teaches all the limitations of claim 1. In addition, Sakano teaches wherein the sensor circuit comprises: a first detection electrode that is provided on a detection surface side of the semiconductor layer, and coupled to the one end of the first photodiode (Figure 5, 161 and 200); and a second detection electrode that is provided adjacent to the first detection electrode (Figure 1, pixel array 141 (and thus a plurality of adjacent photodiodes)), and coupled to the one end of the second photodiode (Figure 1, pixel array).
Sakano does not appear to specifically disclose a gain ratio of a gain of the first detection circuit to that of the second detection circuit is set to be substantially equal to a reciprocal of an area ratio of an area of the first detection electrode to that of the second detection electrode.
However, in a related field of endeavor, Blessinger teaches an array of pixel circuits (abstract) and further teaches a gain ratio of a gain of the first detection circuit to that of the second detection circuit is set to be substantially equal to a reciprocal of an area ratio of an area of the first detection electrode to that of the second detection electrode ([0011], different size detector and gain is proportional to the responsive area).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to have different size detector areas as taught by Blessinger in [0011] in order to provide an extended dynamic range.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakano, Madurawe and Onishi as applied to claim 1 above, and further in view of Chen U.S. Patent Publication No. 2018/0349666 (hereinafter Chen).
Consider claim 4, Sakano, Madurawe and Onishi teach all the limitations of claim 1. In addition, Sakano teaches wherein the sensor circuit comprises: a first detection electrode that is provided on a detection surface side of the semiconductor layer, and coupled to the one end of the first photodiode (Figure 5, 161 and 200); and a second detection electrode that is provided adjacent to the first detection electrode, and coupled to the one end of the second photodiode (Figure 5, 161 and 200. Figure 1, pixel array 141 (and thus a plurality of adjacent photodiodes)).
Sakano does not appear to specifically disclose the second detection electrode is provided so as to surround the first detection electrode.
However, in a related field of endeavor, Chen teaches common-mode noise eliminated in the differential amplifier in [0027] and further teaches the second detection electrode is provided so as to surround the first detection electrode (Figure 7 and [0042], reference electrode 713 and sensing electrode 711).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a reference electrode as taught by Chen with the benefit that the reference sensing signal 720 received by the differential amplifier 223 illustrated in FIG. 7 may also contribute to reducing the DC offset component contained in the differential input signal as suggested in [0043].
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakano and Onishi
Consider claim 6, Sakano teaches a detection device comprising: a sensor circuit provided with a first photodiode having a first detection electrode and a first power supply electrode with a semiconductor layer therebetween (Figures 5-6, Vmid, 161-163 and 200); a second detection electrode adjacent to the first detection electrode (Figure 1, pixel array 141 (and thus a plurality of adjacent electrodes)); and a signal detector configured to acquire a detection value corresponding to a signal output from the sensor circuit (Figure 1, 43, 48, 200 (see also figure 6)), wherein one end of the first detection electrode and the first power supply electrode is coupled to the signal detector (Figures 5-6, 200 and 161) and another end of the first detection electrode and the first power supply electrode is coupled to a reference potential (Figures 5-6, 162 and Vmid), the second detection electrode is coupled to the signal detector (Figure 5, 200 and 161. Figure 1, pixel array 141).
Sakano does not appear to specifically disclose the signal detector is configured to output a difference value between a detection value acquired by the first detection electrode and a detection value acquired by the second detection electrode.
However, Onishi teaches the signal detector is configured to output a difference value between a detection value acquired by the first detection electrode and a detection value acquired by the second detection electrode (Figure 5 and [0069-0070]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a difference value as taught by Onishi in order to improves common mode rejection ratio and power supply rejection ration as suggested in [0069].
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Prior arts do not appear to disclose the states of the switches mentioned in claim 5 in combination to others limitations in the claim and any intervening claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see Madurawe above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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