DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (Pub. No.: US 2020/0005701) in view of Sun (Pub. No.: US 2017/0147127) and Kang et al. (Pub. No.: KR 20130064510) and further in view of Chan (Pub. No.: US 2016/0365034).
Consider claim 1, Chen discloses a display panel (paragraph [0038], Fig. 3, display panel 10), comprising:
a display region and a peripheral region (paragraph [0038], Fig. 3, display panel 10 includes a display area and a non-display area),
wherein the display region comprises a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units (paragraph [0039], Fig. 3, sub-pixels are arranged in an array, e.g., a row of sub-pixels are connected to one of the multiple scanning lines, and a column of sub-pixels are connected to one of the multiple data cables), and the peripheral region comprises a gate drive circuit (paragraph [0038], Fig. 3, multiple first shift registers 201 and multiple second shift registers 202);
the display region further comprises a plurality of gate lines and a plurality of data lines (paragraph [0039], Fig. 3, sub-pixels are arranged in an array, e.g., a row of sub-pixels are connected to one of the multiple scanning lines, and a column of sub-pixels are connected to one of the multiple data cables),
the gate drive circuit comprises a plurality of shift register units arranged in sequence (paragraph [0038], Fig. 3, multiple first shift registers 201 and multiple second shift registers 202), and the plurality of gate lines are electrically connected with the plurality of shift register units (paragraph [0038], Fig. 3, scanning lines 30 connected to a respective one of the multiple shift registers);
the gate drive circuit comprises two shift-register-unit scanning groups (paragraph [0038], Fig. 3, multiple first shift registers 201 and multiple second shift registers 202),
in the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit are formed (paragraph [0038], Fig. 3, (k+1)th being (First or Second) shift register 2 and (k)th being (First or Second) shift register 1 of First shift register 201 and Second shift register 202, respectively,
the (k)th shift register unit in one of the shift-register-unit scanning groups and the (k+1)th shift register unit in another of the shift-register-unit scanning groups are connected (paragraph [0057], Figs. 3, 10, (k)th being Second shift register 1 of Second shift registers 202 (including second trigger signal input end INF2) is connected to (k+1)th being First shift register n of first shift registers 201 (including first trigger signal output end NEXT1)),
the shift register unit is connected with clock signals (paragraph [0067], Fig. 10, the display panel further includes a first clock signal line CLK1 and a second clock signal line CLK2).
Chen does not specifically disclose in the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit form one shift register unit group.
Sun discloses in the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit form one shift register unit group (paragraph [0027], Fig. 1, each stage of shift registers 131 in each of the N groups of shift registers are sequentially electrically connected with each other in series).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace multiple first shift registers and multiple second shift registers as disclosed by Chen with the N groups of shift registers as taught by Sun to provide for each of the plurality of stages of shift registers to be arranged to correspond to and electrically connect to one of the plurality of scan lines (Sun, paragraph [0027]).
The combination of Chen and Sun does not specifically disclose two of the subpixel units adjacent to each other in one of the rows and connected to different gate lines are connected to a same data line respectively and each of the plurality of data line has a zigzag wiring shape.
Kang discloses two of the subpixel units adjacent to each other in one of the rows (paragraph [0027], Fig. 2, subpixels B and subpixel R located between data lines DL1 and DL2 on first row) and connected to different gate lines (paragraph [0027], Fig. 2, subpixel B connected to gate line GL1 and subpixel R connected to gate line GL2) are connected to a same data line respectively (Fig. 2, each subpixel B and R are connected to data line DL2) and each of the plurality of data line has a zigzag wiring shape (paragraph [0024], Fig. 2, each data line crossing into adjacent columns and back in each row forming a zigzag wiring shape).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the data line arrangement as disclosed by the combination of Chen and Sun with the zigzag wiring shape as taught by Kang to dispose pixels between the odd-numbered gate lines and the even-numbered gate lines and between the adjacent data lines (Kang, paragraph [0027]).
The combination of Chen, Sun, and Kang does not specifically disclose a ratio of a time during which each of the clock signals is at a high level to a period in each of clock signals is less than 50%.
Chan discloses a ratio of a time during which each of the clock signals is at a high level to a period in each of clock signals is less than 50% (paragraphs [0035], [0042], Fig. 4A, the duty cycle of the clock signals C1-C8 (i.e. the ratio of the duration of high voltage to the full duration in one period of the clock signals C1-C8) is less than 50 percent).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace clock signals as disclosed by the combination of Chen, Sun, and Kang with the clock signals as taught by Chan to order to solve display issues such as spot mura defects, line mura defects or noise interference of the display apparatus, thereby improving the image display quality (Chan, paragraph [0042]).
Consider claim 2, the combination of Chen, Sun, and Chan does not specifically disclose wherein one gate line is provided at each of two sides of each row of subpixel units, and each row of subpixel units is connected with two gate lines respectively provided at the two sides of each row of subpixel units.
Kang discloses wherein one gate line is provided at each of two sides of each row of subpixel units (paragraph [0027], Fig. 2, pixels PX are disposed between the odd-numbered gate lines and the even-numbered gate lines), and each row of subpixel units is connected with two gate lines respectively provided at the two sides of each row of subpixel units (paragraph [0031], Fig. 2, first transistor TR1 included in the first sub-pixel SPX1 is connected to one of the gate lines GL1 to GL2n).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the scanning lines as disclosed by the combination of Chen, Sun, and Chan with the gate lines as taught by Kang to dispose pixels between the odd-numbered gate lines and the even-numbered gate lines (Kang, paragraph [0027]).
Consider claim 3, the combination of Chen, Sun, and Chan does not specifically disclose wherein the plurality of subpixel units connected with the same data line in sequence have at least a first color and a second color.
Kang discloses wherein the plurality of subpixel units connected with the same data line in sequence have at least a first color and a second color (paragraphs [0040], [0065], Fig. 2, colors of the color filters CF included in the first sub-pixel SPX1 and the second sub-pixel SPX2 may be different from each other).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the subpixels as disclosed by the combination of Chen, Sun, and Chan with the subpixels as taught by Kang to allow for three consecutive sub-pixels included in the same pixel row include red, green, and blue color filters, respectively (Kang, paragraph [0065]).
Consider claim 4, the combination of Chen, Sun, and Kang does not specifically disclose wherein, in the shift-register-unit scanning groups, every two adjacent shift register unit groups are not cascaded.
Chan discloses wherein, in the shift-register-unit scanning groups, every two adjacent shift register unit groups are not cascaded (paragraph [0045], Fig. 6, shift registers 610(1)-610(N) respectively generate scan signals OUT(1)-OUT(N) and scan signals OUT(1)-OUT(8) are respectively inputted to the 9th to 16th stage shift registers 610(9)-610(16); thus, every two adjacent shift register unit groups are not cascaded).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace multiple first shift registers and multiple second shift registers as disclosed by the combination of Chen, Sun, and Kang with shift registers as taught by Chan to provide outputs to non-adjacent shift registers (Chan, Fig. 6, paragraph [0045]).
Consider claim 5, the combination of Chen, Sun, and Kang does not specifically disclose wherein the shift register unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first electrode of the first transistor is connected with the clock signal, and a second electrode of the first transistor is connected with a first electrode of the second transistor; a first electrode of the third transistor, a second electrode of the fourth transistor and a gate electrode of the first transistor are connected with a pull-up node; and a first electrode of the fourth transistor is connected with a gate electrode of the fourth transistor.
Chan discloses wherein the shift register unit comprises a first transistor (paragraph [0039], Fig. 3, transistor M3), a second transistor (paragraph [0041], Fig. 3, transistor M13), a third transistor (paragraph [0041], Fig. 3, transistor M12), a fourth transistor (paragraph [0040], Fig. 3, transistor M7), a first electrode of the first transistor is connected with the clock signal (paragraph [0039], Fig. 3, first source/drain of the transistor M3 is configured to receive the clock signal), and a second electrode of the first transistor is connected with a first electrode of the second transistor (Fig. 3, second source/drain of the transistor M3 connected to second source/drain of the transistor M13 at Y node); a first electrode of the third transistor, a second electrode of the fourth transistor and a gate electrode of the first transistor are connected with a pull-up node (Fig. 3, electrodes of transistor M12, transistor M7 and transistor M3 are connected at Node X which is connected to pull-up unit 320; thus, a pull-up node); and a first electrode of the fourth transistor is connected with a gate electrode of the fourth transistor (Fig. 3, first electrode of M7 connected to gate electrode of M7 via transistor M6 on status).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the shift register unit as disclosed by the combination of Chen, Sun, and Kang with the shift register unit as taught by Chan to output the scan signal (Chan, paragraph [0039]).
Consider claim 6, the combination of Chen, Sun, Kang, and Chan discloses wherein the shift register unit further comprises a storage capacitor (Chan, paragraph [0039], Fig. 3, capacitor Cx), the storage capacitor has an end connected with the gate electrode of the first transistor and the pull-up node (Chan, paragraph [0039], Fig. 3, first terminal of the capacitor Cx is coupled to the gate of the transistor M3 at node X) and another end connected with a second electrode of the first transistor (Chan, paragraph [0039], Fig. 3, second terminal of the capacitor Cx is coupled to the second source/drain of the transistor M3); a gate electrode of the third transistor is connected with a gate electrode of the second transistor (Chan, Fig. 3, gate electrode of transistor M12 connected to gate electrode of transistor M13); a second electrode of the second transistor is connected with a low level signal (Chan, Fig. 3, source/drain of the transistor M13 connected to VGL2).
Consider claim 7, the combination of Chen, Sun, Kang, and Chan discloses wherein the first electrode of the fourth transistor is connected with an output end of the shift register unit of a previous row, to receive a scanning signal as an input signal and an input control signal (Chan, paragraph [0048], Figs. 2, 3, second source/drain of the transistor M7 connected with the input signal IN1 that is the scan signal OUT(i−8)), and a gate electrode of the second transistor and a gate electrode of the third transistor are connected with an output end of the shift register unit of a next row to receive a scanning signal as an output pull-down control signal (Chan, Fig. 2, 3, gate electrode of transistor M12 and gate electrode of transistor M13 connected (via transistors M2 and M11) with input signal IN2 that is the scan signal OUT(i+8)).
Consider claim 8, the combination of Chen, Sun, Kang, and Chan discloses wherein the shift-register-unit scanning groups comprises 16 shift register units (Chan, paragraph [0045], Fig. 6, N stage shift registers 610(1)-610(N), where N is a multiple of 16), and in the shift-register-unit scanning groups, (k+1)th and (k+2)th shift register units are not cascaded (Chan, Fig. 6, shift registers 610(1) and 610(3) are not cascaded), and k is 1, 3, 5, 7, 9, 11, 13 or 15 (Chan, Fig. 6, where N is 1, 3, 5, 7, 9, 11, 13 or 15).
Consider claim 9, the combination of Chen, Sun, Kang, and Chan discloses wherein the clock signals received by the 16 shift register units in the shift-register-unit scanning groups are a first clock signal to a sixteenth clock signal (Chan, paragraph [0045], Fig. 6, clock signals C1-C8 and C1′-C8′ to the corresponding shift registers 610(1)-610(N)), and the first clock signal to the sixteenth clock signal have equal periods and equal duty ratios (paragraph [0042], Fig. 4A, clock period of each of the clock signals C1-C8 is 16 data writing periods H).
Consider claim 16, the combination of Chen, Sun, Kang, and Chan discloses a display device, comprising a display panel according to claim 1 (Chen, paragraph [0107], Fig. 26, display device includes the display panel).
Consider claim 17, the combination of Chen, Sun, and Chan discloses the driving method comprising: providing clock signals to the gate drive circuit to cause the gate drive circuit to generate a scanning signal (paragraph [0067], clock signals for shift registers),
The combination of Chen, Sun, and Chan does not specifically disclose to enable at least two subpixel units of a same color which are connected with a same data line and not adjacent to each other to display successively in timing.
Kang discloses to enable at least two subpixel units of a same color which are connected with a same data line and not adjacent to each other to display successively in timing (Fig. 3, data line DL2 connected to a red subpixel R in pixel row 1, column 4 and a red subpixel R in pixel row 2, column 1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the subpixel arrangement as disclosed by the combination of Chen and Sun with the pixel arrangement as taught by Kang to coordinate a display of a specified color with different colors (Kang, Fig. 2).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,230,180 in view of Chan (Pub. No.: US 2016/0365034).
Instant Application
U.S. Patent No. 12,230,180
1. A display panel, comprising: a display region and a peripheral region, wherein the display region comprises a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units, and the peripheral region comprises a gate drive circuit; the display region further comprises a plurality of gate lines and a plurality of data lines, the gate drive circuit comprises a plurality of shift register units arranged in sequence, and the plurality of gate lines are electrically connected with the plurality of shift register units; the gate drive circuit comprises two shift-register-unit scanning groups, in the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit form one shift register unit group, the (k)th shift register unit in one of the shift-register-unit scanning groups and the (k+1)th shift register unit in another of the shift-register-unit scanning groups are connected, two of the subpixel units adjacent to each other in one of the rows and connected to different gate lines are connected to a same data line respectively and each of the plurality of data line has a zigzag wiring shape, the shift register unit is connected with clock signals, a ratio of a time during which each of the clock signals is at a high level to a period in each of clock signals is less than 50%.
1. A display panel, comprising: a display region and a peripheral region, wherein the display region comprises a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units, and the peripheral region comprises a gate drive circuit; the display region further comprises a plurality of gate lines and a plurality of data lines, the gate drive circuit comprises a plurality of shift register units arranged in sequence, and the plurality of gate lines are electrically connected with the plurality of shift register units; the gate drive circuit comprises two shift-register-unit scanning groups, in the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit form one shift register unit group, the (k)th shift register unit in one of the shift-register-unit scanning groups and the (k+1)th shift register unit in another of the shift-register-unit scanning groups are connected, two of the subpixel units adjacent to each other in one of the rows and connected to different gate lines are connected to a same data line respectively and each of the plurality of data line has a zigzag wiring shape.
The patent fails to disclose the shift register unit is connected with clock signals, a ratio of a time during which each of the clock signals is at a high level to a period in each of clock signals is less than 50%.
Chan discloses the shift register unit is connected with clock signals (paragraph [0035], Fig. 2, clock signals C1-C8 for the corresponding shift registers 210(1)-210(N)), a ratio of a time during which each of the clock signals is at a high level to a period in each of clock signals is less than 50% (paragraphs [0035], [0042], Fig. 4A, the duty cycle of the clock signals C1-C8 (i.e. the ratio of the duration of high voltage to the full duration in one period of the clock signals C1-C8) is less than 50 percent).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the shift registers as disclosed by the patent with the shift registers including clock signals as taught by Chan to order to solve display issues such as spot mura defects, line mura defects or noise interference of the display apparatus, thereby improving the image display quality (Chan, paragraph [0042]).
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 2-20 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 2-20 of prior U.S. Patent No. 12,230,180. This is a statutory double patenting rejection.
Allowable Subject Matter
Claims 10-15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the prior art of reference fails to disclose the first, fifth, ninth, thirteenth, third, seventh, eleventh and fifteenth clock signals are adjacent to each other in sequence in timing; the second, sixth, tenth, fourteenth, fourth, eighth, twelfth and sixteenth clock signals are adjacent to each other in sequence in timing; and the first and second clock signals differ in timing by 8 time units.
Regarding claim 18, the prior art of reference fails to disclose driving F subpixel units in a Bth driving group in an order of Ad=B+(d-1)xG.
Regarding claim 19, the prior art of reference fails to disclose using a least common multiple of G1 and G2 as G.
The remaining claims are objected to due to their dependency to objected claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miyake (Pub. No.: US 2014/0023173) discloses a duty ratio of the clock signals CLK1 to CLK4 is 25%.
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/Gerald Johnson/
Primary Examiner, Art Unit 3797