DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 06/09/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/09/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 21 and 26 recite the limitation " the fourth electrode" in lines 1 and 2. There is insufficient antecedent basis for this limitation in the claim.
It appears the applicant intended to reference “the fourth transistor” while constructing these claim limitations. Accordingly, the claims were examined under this pretense.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 16, 22, 27, and 29-33 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (Pub. No.: KR 20050112838 A) in view of Sang (Pub. No.: US 2016/0314736) and further in view of Chan (Pub. No.: US 2016/0365034).
Consider claim 1, Shin discloses a display panel (paragraph [0024], Fig. 1, display panel), comprising:
a display region (paragraph [0024], Fig. 1, display area 100) and a peripheral region (paragraph [0024], Fig. 1, peripheral area outside display area 100),
wherein the display region comprises a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units (paragraph [0025], Fig. 1, pixel region 110 is defined by two neighboring selected scan lines and two neighboring data lines, and two pixels 111 and 112 are formed in the pixel region 110), and the peripheral region comprises a gate drive circuit (paragraph [0026], Fig. 1, light emitting scan driving unit 300 for driving);
the display region further comprises a plurality of gate lines and a plurality of data lines (paragraph [0025], Fig. 1, data lines (D1~Dn) extend in the column direction and emission scanning line (E11E1 m, E21E2m) extends in the horizontal direction for each pixel, respectively),
the gate drive circuit comprises a plurality of shift register units arranged in sequence (paragraph [0054], Fig. 6, i-th flip-flop (FF)2i) and (i+1)th flip-flop (FF)2(i+1)) acting as shift registers arranged in sequence),
the gate drive circuit comprises two shift-register-unit scanning groups (paragraph [0054], Fig. 6, light emitting scan driver 300 includes m flip-flops (FF)21FF2m) And m inverters (INV21~INV2m), and acts as a shift register),
a (k+1)th shift register unit and a (k)th shift register unit of a same shift-register-unit scanning groups are cascaded to form one shift register unit group ((Fig. 9, output of i-th flip-flop (FF3i) is connected to input of (i+1)-th flip-flop (FF3(i+1))) and paragraph [0054], Fig. 6, cascaded i-th flip-flop (FF)2i) and (i+1)th flip-flop (FF)2(i+1)) acting as shift registers), gate lines respectively connected to the k(th) shift register unit and the (k+1)th shift register unit of the same shift-register-unit scanning groups drive a same row of subpixel units (paragraph [0072], Fig. 9, The i-th NAND gate (NAND3i) performs a NAND operation on the output signal (SR3i) of the i-th flip-flop (FF3i) and the output signal (SR3(i+1)) of the (i+1)-th flip-flop (FF3(i+1)) to produce an output (e.g., emit1[1]). And the i-th NOR gate (NOR3i) performs a NOR operation on the output signal (SR3i) of the i-th flip-flop (FF3i) and the output signal (SR3(i+1)) of the (i+1)-th flip-flop (FF3(i+1)) and outputs it to the inverter (INV3i) (e.g., emit2[1])), the (k)th shift register unit in one of the shift-register-unit scanning groups and the (k+1)th shift register unit in another of the shift-register-unit scanning groups are connected (Fig. 9, output of i-th flip-flop (FF3i) is connected to input of (i+1)-th flip-flop (FF3(i+1))), two of the subpixel units adjacent to each other in one of the rows (Fig. 1, subpixel 111 and subpixel 112 are adjacent to each other in the same row) and connected to different gate lines are connected to a same data line respectively (Fig. 1, emission scanning line emission scanning line E11 is connected to subpixel 111 while emission scanning line E21 is connected to subpixel 112 and both subpixels are connected data line D1), the two of the subpixel units are provided at sides of the same data line respectively (Fig. 1, both subpixel 111 and subpixel 112 are connected to data line D1), and
the shift register unit is connected with clock signals (Fig. 9, clock signals VCLKb and VCLK connect to the shift register unit),
Shin does not specifically disclose each of the plurality of data line has a zigzag wiring shape.
Sang discloses each of the plurality of data line has a zigzag wiring shape (paragraphs [0060] and [0064] thru [0066], Figs. 2, 3, 7, data line with zigzag wiring shape).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the data line wiring shape as disclosed by Shin with the data line wiring shape as taught by Sang to reduce power consumption (Sang, paragraph [0060]).
The combination of Shin and Sang does not specifically disclose the clock signals comprises a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, an eighth clock signal, a nineth clock signal and a tenth clock signal, the clock signals comprises a plurality of periods, at least one of the plurality of periods comprise a high level of time of period and a low level of time of period, and a duration of the time of period of the low level is larger than a duration of the time of period of the high level, and in one of the plurality of periods, an overlap duration of a high level of the first clock signal and a high level of the second clock signal is longer than an overlap duration of the high level of the second clock signal and a low level of the first clock signal; an overlap duration of the high level of the second clock signal and a high level of the third clock signal is longer than an overlap duration of the high level of the third clock signal and a low level of the second clock signal, and an overlap duration of the high level of the third clock signal and a high level of the fourth clock signal is longer than an overlap duration of the high level of the fourth clock signal and a low level of the third clock signal.
Chan discloses the clock signals comprises a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, an eighth clock signal, a nineth clock signal and a tenth clock signal (paragraph [0045], Fig. 6, clock signal lines L1-L8 and L1′-L8′ are configure to respectively provide clock signals C1-C8 and C1′-C8′ to the corresponding shift registers 610(1)-610(N)), the clock signals comprises a plurality of periods (paragraph [0050], Fig. 8A, starting signal STV falls to low voltage from high voltage, the clock signals C1-C8 sequentially rise to high voltage and then the clock signals C1-C8 sequentially fall to low voltage. Note, STV′ and C1′-C8′ functionally perform the same), at least one of the plurality of periods comprise a high level of time of period and a low level of time of period (Fig. 8A, clock C1 with high level of time of period and a low level of time of period), and a duration of the time of period of the low level is larger than a duration of the time of period of the high level (paragraph [0050], Fig. 8A, the high level duration is shorter than the low level duration), and in one of the plurality of periods, an overlap duration of a high level of the first clock signal and a high level of the second clock signal is longer than an overlap duration of the high level of the second clock signal and a low level of the first clock signal (Fig. 8A, overlap duration of high level signal of clock C1 and high level signal of clock C2 is longer than an overlap duration of the high level signal of clock C2 and a low level of clock C1 signal); an overlap duration of the high level of the second clock signal and a high level of the third clock signal is longer than an overlap duration of the high level of the third clock signal and a low level of the second clock signal (Fig. 8A, overlap duration of high level signal of clock C2 and high level signal of clock C3 is longer than an overlap duration of the high level signal of clock C3 and a low level of clock C2 signal), and an overlap duration of the high level of the third clock signal and a high level of the fourth clock signal is longer than an overlap duration of the high level of the fourth clock signal and a low level of the third clock signal (Fig. 8A, overlap duration of high level signal of clock C3 and high level signal of clock C4 is longer than an overlap duration of the high level signal of clock C4 and a low level of clock C3 signal).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace clock signals as disclosed by the combination of Shin and Sang with the clock signals as taught by Chan to provide shift registers 610(1)-610(N) respectively to generate scan signals OUT(1)-OUT(N) (Chan, paragraph [0045]).
Consider claim 2, the combination of Shin and Chan does not specifically disclose wherein one gate line is provided at each of two sides of each row of subpixel units, and each row of subpixel units is connected with two gate lines respectively provided at the two sides of each row of subpixel units.
Sang discloses wherein one gate line is provided at each of two sides of each row of subpixel units, and each row of subpixel units is connected with two gate lines respectively provided at the two sides of each row of subpixel units (paragraph [0067], Figs. 4, 7, subpixels arranged on one row Li may be connected alternately to an odd-numbered gate line and to an even-numbered gate line).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the gate line structure as disclosed by the combination of Shin and Chan with the gate line structure as taught by Sang to provide a first gate line G1 connected to odd-numbered subpixels among the subpixels arranged on the first row L1, and a second gate line G2 connected to even-numbered subpixels among the subpixels arranged on the first row L1 (Sang, paragraph [0067]).
Consider claim 3, the combination of Shin, Sang, and Chan discloses wherein the plurality of subpixel units connected with the same data line in sequence have at least a first color and a second color (paragraph [0031], Fig. 2, two pixels (111ij, 112ij) of a pixel region (110ij) formed by a data line (Dj) where each emit light of R and G colors).
Consider claim 7, the combination of Shin, Sang, and Chan discloses wherein, and a gate electrode of the second transistor and a gate electrode of the third transistor are connected with an output end of the shift register unit of a next row to receive a scanning signal as an output pull-down control signal (Chan, Fig. 2, 3, gate electrode of transistor M12 and gate electrode of transistor M13 connected (via transistors M2 and M11) with input signal IN2 that is the scan signal OUT(i+8)).
Consider claim 16, the combination of Shin, Sang, and Chan discloses a display device, comprising a display panel according to claim 1 (Shin, paragraph [0024], Fig. 1, display device includes a display panel).
Consider claim 22, the combination of Shin and Sang discloses in each of the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit are cascaded to form one shift register unit group (paragraph [0072], Fig. 9, i-th flip-flop (FF3i) becomes the input signal of the (i+1)-th flip-flop (FF3(i+1))).
The combination of Shin and Sang does not specifically disclose each of the shift-register-unit scanning groups comprises 16 shift register units.
Chan discloses each of the shift-register-unit scanning groups comprises 16 shift register units (paragraph [0045], Fig. 6, N stage shift registers 610(1)-610(N), where N is a multiple of 16).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the shift register unit as disclosed by the combination of Shin and Sang with the shift register unit as taught by Chan to allow each of the scan signals OUT(9)-OUT(N−8) for input to the shift registers previous four stage shift register thereto and next four stage shift register thereto (Chan, paragraph [0045]).
Consider claim 27, the combination of Shin and Chan does not specifically disclose wherein adjacent data lines have reversed polarity, and two adjacent subpixel units connected to a same data line and extending in a direction of the gate line have a same polarity.
Sang discloses wherein adjacent data lines have reversed polarity (paragraph [0068], Fig. 7, adjacent data lines S(4k+1) and S(4k+2) have reversed polarity), and two adjacent subpixel units connected to a same data line and extending in a direction of the gate line have a same polarity ((paragraph [0068], Fig. 7, in row L1, green G subpixel and blue B subpixel connected to data line S(4k+1) are both positive polarity).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the data lines as disclosed by combination of Shin and Chan with the data lines as taught by Sang in order that a polarity relationship of the data voltages supplied to the data lines is equally maintained among the data lines (Sang, paragraph [0068]).
Consider claim 29, Shin does not specifically disclose wherein one gate line is provided at each of two sides of each row of subpixel units, and each row of subpixel units is connected with two gate lines respectively provided at the two sides of each row of subpixel units.
Sang discloses wherein one gate line is provided at each of two sides of each row of subpixel units, and each row of subpixel units is connected with two gate lines respectively provided at the two sides of each row of subpixel units (paragraph [0067], Figs. 4, 7, subpixels arranged on one row Li may be connected alternately to an odd-numbered gate line and to an even-numbered gate line).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the gate line structure as disclosed by Shin with the gate line structure as taught by Sang to provide a first gate line G1 connected to odd-numbered subpixels among the subpixels arranged on the first row L1, and a second gate line G2 connected to even-numbered subpixels among the subpixels arranged on the first row L1 (Sang, paragraph [0067]).
The combination of Shin and Sang does not specifically disclose in one period of the clock signal, an overlap duration of a high level of the first clock signal and a high level of the second clock signal is longer than an overlap duration of the high level of the second clock signal and a low level of the first clock signal; an overlap duration of the high level of the second clock signal and a high level of the third clock signal is longer than an overlap duration of the high level of the third clock signal and a low level of the second clock signal, and an overlap duration of the high level of the third clock signal and a high level of the fourth clock signal is longer than an overlap duration of the high level of the fourth clock signal and a low level of the third clock signal.
Chan discloses in one period of the clock signal, an overlap duration of a high level of the first clock signal and a high level of the second clock signal is longer than an overlap duration of the high level of the second clock signal and a low level of the first clock signal (Fig. 8A, overlap duration of high level signal of clock C1 and high level signal of clock C2 is longer than an overlap duration of the high level signal of clock C2 and a low level of clock C1 signal); an overlap duration of the high level of the second clock signal and a high level of the third clock signal is longer than an overlap duration of the high level of the third clock signal and a low level of the second clock signal (Fig. 8A, overlap duration of high level signal of clock C2 and high level signal of clock C3 is longer than an overlap duration of the high level signal of clock C3 and a low level of clock C2 signal), and an overlap duration of the high level of the third clock signal and a high level of the fourth clock signal is longer than an overlap duration of the high level of the fourth clock signal and a low level of the third clock signal (Fig. 8A, overlap duration of high level signal of clock C3 and high level signal of clock C4 is longer than an overlap duration of the high level signal of clock C4 and a low level of clock C3 signal).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the shift register unit as disclosed by the combination of Shin and Sang with the shift register unit as taught by Chan to output the scan signal (Chan, paragraph [0039]).
Consider claim 30, the combination of Shin and Sang does not specifically disclose wherein the shift register unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first electrode of the first transistor is connected with the clock signal, a second electrode of the first transistor is connected with a first electrode of the second transistor; a first electrode of the third transistor, a second electrode of the fourth transistor and a gate electrode of the first transistor are connected with a pull-up node; and a first electrode of the fourth transistor is connected with a gate electrode of the fourth transistor.
Chan discloses wherein the shift register unit comprises a first transistor (paragraph [0039], Fig. 3, transistor M3), a second transistor (paragraph [0041], Fig. 3, transistor M13), a third transistor (paragraph [0041], Fig. 3, transistor M12), a fourth transistor (paragraph [0040], Fig. 3, transistor M7), a first electrode of the first transistor is connected with the clock signal (paragraph [0039], Fig. 3, first source/drain of the transistor M3 is configured to receive the clock signal), a second electrode of the first transistor is connected with a first electrode of the second transistor (Fig. 3, second source/drain of the transistor M3 connected to second source/drain of the transistor M13 at Y node); a first electrode of the third transistor, a second electrode of the fourth transistor and a gate electrode of the first transistor are connected with a pull-up node (Fig. 3, electrodes of transistor M12, transistor M7 and transistor M3 are connected at Node X which is connected to pull-up unit 320; thus, a pull-up node); and a first electrode of the fourth transistor is connected with a gate electrode of the fourth transistor (Fig. 3, first electrode of M7 connected to gate electrode of M7 via transistor M6 on status).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the shift register unit as disclosed by the combination of Shin and Sang with the shift register unit as taught by Chan to output the scan signal (Chan, paragraph [0039]).
Consider claim 31, the combination of Shin, Sang, and Chan discloses wherein the shift register unit further comprises a storage capacitor (Chan, paragraph [0039], Fig. 3, capacitor Cx), the storage capacitor has an end connected with the gate electrode of the first transistor and the pull-up node (Chan, paragraph [0039], Fig. 3, first terminal of the capacitor Cx is coupled to the gate of the transistor M3 at node X) and another end connected with a second electrode of the first transistor (Chan, paragraph [0039], Fig. 3, second terminal of the capacitor Cx is coupled to the second source/drain of the transistor M3); a gate electrode of the third transistor is connected with a gate electrode of the second transistor (Chan, Fig. 3, gate electrode of transistor M12 connected to gate electrode of transistor M13); a second electrode of the second transistor is connected with a low level signal (Chan, Fig. 3, source/drain of the transistor M13 connected to VGL2).
Consider claim 32, the combination of Shin, Sang, and Chan discloses wherein the clock signals comprise a plurality of periods (Chan, paragraph [0050], Fig. 8A, starting signal STV falls to low voltage from high voltage, the clock signals C1-C8 sequentially rise to high voltage and then the clock signals C1-C8 sequentially fall to low voltage. Note, STV′ and C1′-C8′ functionally perform the same), at least one of the plurality of periods comprise a high level of time of period and a low level of time of period (Chan, Fig. 8A, clock C1 with high level of time of period and a low level of time of period), and a duration of the time of period of the low level is larger than a duration of the time of period of the high level (Chan, paragraph [0050], Fig. 8A, the high level duration is shorter than the low level duration).
Consider claim 33, the combination of Shin and Sang discloses in each of the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit are cascaded to form one shift register unit group (paragraph [0072], Fig. 9, i-th flip-flop (FF3i) becomes the input signal of the (i+1)-th flip-flop (FF3(i+1))).
The combination of Shin and Sang does not specifically disclose wherein each of the shift-register-unit scanning groups comprises 16 shift register units.
Chan discloses wherein each of the shift-register-unit scanning groups comprises 16 shift register units (paragraph [0045], Fig. 6, N stage shift registers 610(1)-610(N), where N is a multiple of 16).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the shift register unit as disclosed by the combination of Shin and Sang with the shift register unit as taught by Chan to allow each of the scan signals OUT(9)-OUT(N−8) for input to the shift registers previous four stage shift register thereto and next four stage shift register thereto (Chan, paragraph [0045]).
Claims 4, 6, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Shin, Sang, and Chan in view of Shao et al. (Pub. No.: US 2015/0371716).
Consider claim 4, the combination of Shin and Sang does not specifically disclose wherein the shift register unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first electrode of the first transistor is connected with the clock signal, a second electrode of the first transistor is connected with a first electrode of the second transistor; a first electrode of the third transistor, a second electrode of the fourth transistor and a gate electrode of the first transistor are connected with a pull-up node.
Chan discloses wherein the shift register unit comprises a first transistor (paragraph [0039], Fig. 3, transistor M3), a second transistor (paragraph [0041], Fig. 3, transistor M13), a third transistor (paragraph [0041], Fig. 3, transistor M12), a fourth transistor (paragraph [0040], Fig. 3, transistor M7), a first electrode of the first transistor is connected with the clock signal (paragraph [0039], Fig. 3, first source/drain of the transistor M3 is configured to receive the clock signal), a second electrode of the first transistor is connected with a first electrode of the second transistor (Fig. 3, second source/drain of the transistor M3 connected to second source/drain of the transistor M13 at Y node); a first electrode of the third transistor, a second electrode of the fourth transistor and a gate electrode of the first transistor are connected with a pull-up node (Fig. 3, electrodes of transistor M12, transistor M7 and transistor M3 are connected at Node X which is connected to pull-up unit 320; thus, a pull-up node).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the shift register unit as disclosed by the combination of Shin and Sang with the shift register unit as taught by Chan to output the scan signal (Chan, paragraph [0039]).
The combination of Shin, Sang, and Chan discloses a first electrode of M7 connected to gate electrode of M7 via transistor M6 on status (see Chan, Fig. 3).
The combination of Shin, Sang, and Chan does not specifically disclose a first electrode of the fourth transistor is connected with a gate electrode of the fourth transistor.
Shao discloses a first electrode of the fourth transistor is connected with a gate electrode of the fourth transistor (paragraph [0005], Fig. 1, gate of the first transistor M1 is connected to its source).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the fourth transistor as disclosed by the combination of Shin, Sang, and Chan with the fourth transistor as taught by Shao for receiving an input signal INPUT which is the output signal OUTPUT of the previous stage of shift register unit (Shao, paragraph [0005]).
Consider claim 6, the combination of Shin, Sang, Chan, and Shao discloses wherein the shift register unit further comprises a storage capacitor (Chan, paragraph [0039], Fig. 3, capacitor Cx), the storage capacitor has an end connected with the gate electrode of the first transistor and the pull-up node (Chan, paragraph [0039], Fig. 3, first terminal of the capacitor Cx is coupled to the gate of the transistor M3 at node X) and another end connected with a second electrode of the first transistor (Chan, paragraph [0039], Fig. 3, second terminal of the capacitor Cx is coupled to the second source/drain of the transistor M3); a gate electrode of the third transistor is connected with a gate electrode of the second transistor (Chan, Fig. 3, gate electrode of transistor M12 connected to gate electrode of transistor M13); a second electrode of the second transistor is connected with a low level signal (Chan, Fig. 3, source/drain of the transistor M13 connected to VGL2).
Consider claim 21, the combination of Shin, Sang, and Chan does not specifically disclose wherein a first electrode of the fourth electrode is connected to an output end of the shift register unit of a previous row.
Shao discloses wherein a first electrode of the fourth electrode is connected to an output end of the shift register unit of a previous row (paragraph [0005], Fig. 1, source of the first transistor M1 is connected to a shift trigger signal input terminal 1 for receiving an input signal INPUT which is the output signal OUTPUT of the previous stage of shift register unit).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the fourth transistor as disclosed by the combination of Shin, Sang, and Chan with the fourth transistor as taught by Shao for receiving an input signal INPUT which is the output signal OUTPUT of the previous stage of shift register unit (Shao, paragraph [0005]).
Claims 23-25 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Chan.
Consider claim 23, Shin discloses a display panel (paragraph [0024], Fig. 1, display panel), comprising:
a display region (paragraph [0024], Fig. 1, display area 100) and a peripheral region (paragraph [0024], Fig. 1, peripheral area outside display area 100),
wherein the display region comprises a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units (paragraph [0025], Fig. 1, pixel region 110 is defined by two neighboring selected scan lines and two neighboring data lines, and two pixels 111 and 112 are formed in the pixel region 110), and the peripheral region comprises a gate drive circuit (paragraph [0026], Fig. 1, light emitting scan driving unit 300 for driving);
the display region further comprises a plurality of gate lines and a plurality of data lines (paragraph [0025], Fig. 1, data lines (D1~Dn) extend in the column direction and emission scanning line (E11E1 m, E21E2m) extends in the horizontal direction for each pixel, respectively),
the gate drive circuit comprises a plurality of shift register units arranged in sequence (paragraph [0072], Fig. 9, light-emitting scanning driver (300) composed of (m+1) flip-flops (FF31 to FF3(m+1)), m NAND gates (NAND31 to NAND3m), m NOR gates (NOR31 to NOR3m), and m inverters (INV31 to INV3m), and operates as shift registers arranged in sequence), and the plurality of gate lines are electrically connected with the plurality of shift register units (paragraph [0072], Fig. 9, output signals of the NAND gates (NAND31 to NAND3m) become the light emission signals (emit1[1] to emit1[m]) of the light emission scan lines (E11 to E1m), and the output signals of the NOR gates (NOR31 to NOR3m) are inverted by the inverter (INV31 to INV3m) and become the light emission signals (emit2[1] to emit2[m]) of the light emission scan lines (E21 to E2m));
the gate drive circuit comprises two shift-register-unit scanning groups (paragraph [0072], Fig. 9, i-th flip-flop (FF3i) and (i+1)-th flip-flop (FF3(i+1))),
a (k+1)th shift register unit and a (k)th shift register unit of a same shift-register-unit scanning groups are cascaded to form one shift register unit group (Fig. 9, output of i-th flip-flop (FF3i) is connected to input of (i+1)-th flip-flop (FF3(i+1))), gate lines respectively connected to the k(th) shift register unit and the (k+1)th shift register unit of the same shift-register-unit scanning groups drive a same row of subpixel units (paragraph [0072], Fig. 9, The i-th NAND gate (NAND3i) performs a NAND operation on the output signal (SR3i) of the i-th flip-flop (FF3i) and the output signal (SR3(i+1)) of the (i+1)-th flip-flop (FF3(i+1)) to produce an output (e.g., emit1[1]). And the i-th NOR gate (NOR3i) performs a NOR operation on the output signal (SR3i) of the i-th flip-flop (FF3i) and the output signal (SR3(i+1)) of the (i+1)-th flip-flop (FF3(i+1)) and outputs it to the inverter (INV3i) (e.g., emit2[1])), the (k)th shift register unit in one of the shift-register-unit scanning groups and the (k+1)th shift register unit in another of the shift-register-unit scanning groups are connected (Fig. 9, output of i-th flip-flop (FF3i) is connected to input of (i+1)-th flip-flop (FF3(i+1))), two of the subpixel units adjacent to each other in one of the rows (Fig. 1, subpixel 111 and subpixel 112 are adjacent to each other in the same row) and connected to different gate lines are connected to a same data line respectively (Fig. 1, emission scanning line emission scanning line E11 is connected to subpixel 111 while emission scanning line E21 is connected to subpixel 112 and both subpixels are connected data line D1), and
the shift register unit is connected with clock signals (Fig. 9, clock signals VCLKb and VCLK connect to the shift register unit),
Shin does not specifically disclose the clock signals comprises a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, an eighth clock signal, a nineth clock signal and a tenth clock signal, the clock signals comprises a plurality of periods, at least one of the plurality of periods comprise a high level of time of period and a low level of time of period, and a duration of the low level of time of period is longer than a duration of the high level of time of period.
Chan discloses the clock signals comprises a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, an eighth clock signal, a nineth clock signal and a tenth clock signal (paragraph [0045], Fig. 6, clock signal lines L1-L8 and L1′-L8′ are configure to respectively provide clock signals C1-C8 and C1′-C8′ to the corresponding shift registers 610(1)-610(N)), the clock signals comprises a plurality of periods (paragraph [0050], Fig. 8A, starting signal STV falls to low voltage from high voltage, the clock signals C1-C8 sequentially rise to high voltage and then the clock signals C1-C8 sequentially fall to low voltage. Note, STV′ and C1′-C8′ functionally perform the same), the clock signals comprises a plurality of periods (paragraph [0050], Fig. 8A, starting signal STV falls to low voltage from high voltage, the clock signals C1-C8 sequentially rise to high voltage and then the clock signals C1-C8 sequentially fall to low voltage. Note, STV′ and C1′-C8′ functionally perform the same), at least one of the plurality of periods comprise a high level of time of period and a low level of time of period (Fig. 8A, clock C1 with high level of time of period and a low level of time of period), and a duration of the low level of time of period is longer than a duration of the high level of time of period (paragraph [0050], Fig. 8A, the high level duration is shorter than the low level duration).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace clock signals as disclosed by Shin with the clock signals as taught by Chan to provide shift registers 610(1)-610(N) respectively to generate scan signals OUT(1)-OUT(N) (Chan, paragraph [0045]).
Consider claim 24, Shin does not specifically disclose wherein the shift register unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first electrode of the first transistor is connected to the clock signal, a second electrode of the first transistor is connected to a first electrode of the second transistor, a first electrode of the third transistor, a second electrode of the fourth transistor and a gate electrode of the first transistor are connected to a pull up node; and a first electrode of the fourth transistor is connected to a gate electrode of the fourth transistor, in one of the plurality of periods, an overlap duration of a high level of the first clock signal and a high level of the second clock signal is longer than an overlap duration of the high level of the second clock signal and a low level of the first clock signal; an overlap duration of the high level of the second clock signal and a high level of the third clock signal is longer than an overlap duration of the high level of the third clock signal and a low level of the second clock signal, and an overlap duration of the high level of the third clock signal and a high level of the fourth clock signal is longer than an overlap duration of the high level of the fourth clock signal and a low level of the third clock signal.
Chan discloses wherein the shift register unit comprises a first transistor (paragraph [0039], Fig. 3, transistor M3), a second transistor (paragraph [0041], Fig. 3, transistor M13), a third transistor (paragraph [0041], Fig. 3, transistor M12), a fourth transistor (paragraph [0040], Fig. 3, transistor M7), a first electrode of the first transistor is connected with the clock signal (paragraph [0039], Fig. 3, first source/drain of the transistor M3 is configured to receive the clock signal), a second electrode of the first transistor is connected with a first electrode of the second transistor (Fig. 3, second source/drain of the transistor M3 connected to second source/drain of the transistor M13 at Y node); a first electrode of the third transistor, a second electrode of the fourth transistor and a gate electrode of the first transistor are connected with a pull-up node (Fig. 3, electrodes of transistor M12, transistor M7 and transistor M3 are connected at Node X which is connected to pull-up unit 320; thus, a pull-up node); and a first electrode of the fourth transistor is connected with a gate electrode of the fourth transistor (Fig. 3, first electrode of M7 connected to gate electrode of M7 via transistor M6 on status), in one of the plurality of periods, an overlap duration of a high level of the first clock signal and a high level of the second clock signal is longer than an overlap duration of the high level of the second clock signal and a low level of the first clock signal (Fig. 8A, overlap duration of high level signal of clock C1 and high level signal of clock C2 is longer than an overlap duration of the high level signal of clock C2 and a low level of clock C1 signal); an overlap duration of the high level of the second clock signal and a high level of the third clock signal is longer than an overlap duration of the high level of the third clock signal and a low level of the second clock signal (Fig. 8A, overlap duration of high level signal of clock C2 and high level signal of clock C3 is longer than an overlap duration of the high level signal of clock C3 and a low level of clock C2 signal), and an overlap duration of the high level of the third clock signal and a high level of the fourth clock signal is longer than an overlap duration of the high level of the fourth clock signal and a low level of the third clock signal (Fig. 8A, overlap duration of high level signal of clock C3 and high level signal of clock C4 is longer than an overlap duration of the high level signal of clock C4 and a low level of clock C3 signal).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the shift register unit as disclosed by Shin with the shift register unit as taught by Chan to output the scan signal (Chan, paragraph [0039]).
Consider claim 25, Shin does not specifically disclose wherein the shift register unit further comprises a storage capacitor, the storage capacitor has an end connected with the gate electrode of the first transistor and the pull-up node and another end connected with a second electrode of the first transistor; a gate electrode of the third transistor is connected with a gate electrode of the second transistor; a second electrode of the second transistor is connected with a low level signal.
Chan discloses wherein the shift register unit further comprises a storage capacitor (paragraph [0039], Fig. 3, capacitor Cx), the storage capacitor has an end connected with the gate electrode of the first transistor and the pull-up node (paragraph [0039], Fig. 3, first terminal of the capacitor Cx is coupled to the gate of the transistor M3 at node X) and another end connected with a second electrode of the first transistor (paragraph [0039], Fig. 3, second terminal of the capacitor Cx is coupled to the second source/drain of the transistor M3); a gate electrode of the third transistor is connected with a gate electrode of the second transistor (Fig. 3, gate electrode of transistor M12 connected to gate electrode of transistor M13); a second electrode of the second transistor is connected with a low level signal (Fig. 3, source/drain of the transistor M13 connected to VGL2).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the shift register unit as disclosed by Shin with the shift register unit as taught by Chan to output the scan signal (Chan, paragraph [0039]).
Consider claim 26, the combination of Shin and Chan discloses the combination of Shin, Sang, and Chan discloses wherein a first electrode of the fourth electrode (Chan, Fig. 3, transistor M7 connection to node X) is connected to an output end of the shift register unit of a previous row (Chan, paragraph [0038], Figs. 2, 3, If the shift register 210(i) is one of the 5.sup.th-(N−4).sup.th stage shift register 210(5)-210(N−4) (i.e., i is an integer from 5 to (N−4)), the input signal IN1 is the scan signal OUT(i−4) outputted by the (i−4).sup.th stage shift register 210(i−4) (i.e., shift register unit of a previous row), and the input signal IN2 is the scan signal OUT(i+4) outputted by the (i+4).sup.th stage shift register 210(i+4)).
Consider claim 28, Shin discloses a display panel (paragraph [0024], Fig. 1, display panel), comprising:
a display region (paragraph [0024], Fig. 1, display area 100) and a peripheral region (paragraph [0024], Fig. 1, peripheral area outside display area 100),
wherein the display region comprises a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units (paragraph [0025], Fig. 1, pixel region 110 is defined by two neighboring selected scan lines and two neighboring data lines, and two pixels 111 and 112 are formed in the pixel region 110), and the peripheral region comprises a gate drive circuit (paragraph [0026], Fig. 1, light emitting scan driving unit 300 for driving);
the display region further comprises a plurality of gate lines and a plurality of data lines (paragraph [0025], Fig. 1, data lines (D1~Dn) extend in the column direction and emission scanning line (E11E1 m, E21E2m) extends in the horizontal direction for each pixel, respectively),
the gate drive circuit comprises a plurality of shift register units arranged in sequence (paragraph [0054], Fig. 6, i-th flip-flop (FF)2i) and (i+1)th flip-flop (FF)2(i+1)) acting as shift registers arranged in sequence), and the plurality of gate lines are electrically connected with the plurality of shift register units (paragraph [0072], Fig. 9, output signals of the NAND gates (NAND31 to NAND3m) become the light emission signals (emit1[1] to emit1[m]) of the light emission scan lines (E11 to E1m), and the output signals of the NOR gates (NOR31 to NOR3m) are inverted by the inverter (INV31 to INV3m) and become the light emission signals (emit2[1] to emit2[m]) of the light emission scan lines (E21 to E2m));
the gate drive circuit comprises two shift-register-unit scanning groups (paragraph [0054], Fig. 6, light emitting scan driver 300 includes m flip-flops (FF)21FF2m) And m inverters (INV21~INV2m), and acts as a shift register),
a (k+1)th shift register unit and a (k)th shift register unit of a same shift-register-unit scanning groups are cascaded to form one shift register unit group (paragraph [0054], Fig. 6, cascaded i-th flip-flop (FF)2i) and (i+1)th flip-flop (FF)2(i+1)) acting as shift registers), gate lines respectively connected to the k(th) shift register unit and the (k+1)th shift register unit of the same shift-register-unit scanning groups drive a same row of subpixel units (paragraph [0072], Fig. 9, The i-th NAND gate (NAND3i) performs a NAND operation on the output signal (SR3i) of the i-th flip-flop (FF3i) and the output signal (SR3(i+1)) of the (i+1)-th flip-flop (FF3(i+1)) to produce an output (e.g., emit1[1]). And the i-th NOR gate (NOR3i) performs a NOR operation on the output signal (SR3i) of the i-th flip-flop (FF3i) and the output signal (SR3(i+1)) of the (i+1)-th flip-flop (FF3(i+1)) and outputs it to the inverter (INV3i) (e.g., emit2[1])), the (k)th shift register unit in one of the shift-register-unit scanning groups and the (k+1)th shift register unit in another of the shift-register-unit scanning groups are connected (Fig. 9, output of i-th flip-flop (FF3i) is connected to input of (i+1)-th flip-flop (FF3(i+1))), two of the subpixel units adjacent to each other in one of the rows (Fig. 1, subpixel 111 and subpixel 112 are adjacent to each other in the same row) and connected to different gate lines are connected to a same data line respectively (Fig. 1, emission scanning line emission scanning line E11 is connected to subpixel 111 while emission scanning line E21 is connected to subpixel 112 and both subpixels are connected data line D1), and
Shin does not specifically disclose the clock signals comprises a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, an eighth clock signal, a nineth clock signal and a tenth clock signal.
Chan discloses the clock signals comprises a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, an eighth clock signal, a nineth clock signal and a tenth clock signal (paragraph [0045], Fig. 6, clock signal lines L1-L8 and L1′-L8′ are configure to respectively provide clock signals C1-C8 and C1′-C8′ to the corresponding shift registers 610(1)-610(N)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace clock signals as disclosed by Shin with the clock signals as taught by Chan to provide shift registers 610(1)-610(N) respectively to generate scan signals OUT(1)-OUT(N) (Chan, paragraph [0045]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Shin and Chan in view of Shao.
Consider claim 26, the combination of Shin and Chan does not specifically disclose wherein a first electrode of the fourth electrode is connected to an output end of the shift register unit of a previous row.
Shao discloses wherein a first electrode of the fourth electrode is connected to an output end of the shift register unit of a previous row (paragraph [0005], Fig. 1, source of the first transistor M1 is connected to a shift trigger signal input terminal 1 for receiving an input signal INPUT which is the output signal OUTPUT of the previous stage of shift register unit).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the fourth transistor as disclosed by the combination of Shin and Chan with the fourth transistor as taught by Shao for receiving an input signal INPUT which is the output signal OUTPUT of the previous stage of shift register unit (Shao, paragraph [0005]).
Conclusion
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/Gerald Johnson/
Primary Examiner, Art Unit 3797
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