Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in thefile.
Claims 1-20 are present for examination.
Claim Objections
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6, 13, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites ‘each event’ in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites ‘each event’ in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites ‘each event’ in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Olbrich et al. (US 20160034227 A1) in view of Hwang et al. (US 20050248992 A1).
Regarding claims 1, 8, and 15: Olbrich discloses a flash storage controller and flash memory (FIG. 3) comprising a deserializer (deserializer within the host of 1801 and port interface 310 in direct communication with Host, par. 243, FIG. 3 and 18) configured to deserialize data received from an external device, a buffer memory (flash buffer e.g., 308, FIG. 3) configured to store the data, and a data loader (Flash HEMi e.g., 307, FIG. 3) configured to generate a control signal based on the data (control signals 708 of Flash HEMi, FIG. 9), wherein the data comprises control information associated with implementing a hardware algorithm (data can be an arbitration algorithm to handle the hardware of the device, par. 335).
Olbrich does not disclose a storage device comprising a nonvolatile memory device comprising a memory cell array, a voltage generator, a row decoder, and a page buffe.
Hwang does disclose a flash semiconductor memory device (100, par. 88, FIG. 13) comprising: comprising a memory cell array (cell array memory 110, FIG. 13), a voltage generator (voltage generator 140, FIG. 13), a row decoder (X-decoder 141, FIG. 13), and a page buffer (page buffer 142, FIG. 13).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the nonvolatile memory of Olbrich with the configuration of Hwang to allow the nonvolatile memory of Olbrich to be arranged as described like the claimed invention.
Claim(s) 2, 9, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Olbrich et al. (US 20160034227 A1) in view of Hwang et al. (US 20050248992 A1), in further view of Arase (US 5812457 A).
Regarding claims 2, 9, and 17: Olbrich does not disclose the hardware algorithm comprises at least information about a sequence of applying voltage to word lines and information about a step of voltage to be applied to the word lines.
Arase discloses a semiconductor NAND type flash memory (FIG. 3) where control signals to the memory device (control signals e.g., ΦP, FIG. 2 and 3) that control the programming voltage to be applied to selected word lines, (col. 3 ll. 20-23), and the word line programming voltage can be incremented in predetermined steps (col .11 ll. 43-50).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Olbrich and Hwang with the configuration of Arase to allow the deserialized data that controls the memory device of Olbrich to control the programming voltage like the claimed invention.
Claim(s) 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Olbrich et al. (US 20160034227 A1) in view of Hwang et al. (US 20050248992 A1), in further view of Gopalakrishnan et al. (US 20140029331 A1).
Regarding claims 3 and 10: Olbrich does not disclose the storage device, wherein the deserializer is further configured to receive the data from the external device through N channels and to divide the data into M pieces per channel by deserializing the data into NxM channels.
Gopalakrishnan does disclose a memory device with multi-mode deserializer (FIG. 2) configured for serial to parallel data conversion allowing for a number of input channels and a plurality of output channels to match an NxM channel ratio (par. 18 and 25).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the deserializers of the system of Olbrich and Hwang with the configuration of Gopalakrishnan to allow the deserializers to have the channel input and output relationship as the claimed invention.
Regarding claim 10: Olbrich does not disclose a method of operating the storage device where a number of the plurality of channels is one less than a number of bank memories included in the buffer memory.
Gopalakrishnan does disclose a memory device with multi-mode deserializer (FIG. 2) configured for serial to parallel data conversion allowing for a number of input channels and a plurality of output channels to match an NxM channel ratio (par. 18 and 25).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a range for number of deserializer channels based on the chosen number of bank memories since it has been held that where the general conditions of a claim are disclosed in the prior art the optimum or workable ranges involves only routine skill in the art.
Claim(s) 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Olbrich et al. (US 20160034227 A1) in view of Hwang et al. (US 20050248992 A1), in further view of Gopalakrishnan et al. (US 20140029331 A1), in further view of Morrison et al. (US 20120221882 A1).
Regarding claims 4 and 11: Olbrich does not disclose a clock frequency of data output to the buffer memory corresponds to a value obtained by dividing a clock frequency of data input to the deserializer by a number of the M pieces.
Morrison does disclose a method of reducing latency in serializer-deserializers links of memory devices comprising a clock frequency of data output to the buffer memory (a system clock speed at the output from, par. 52) corresponds to a value obtained by dividing a clock frequency of data input to the deserializer by a number of the M pieces (from a clock speed of the SerDes clock divided by the value of M units, par. 52).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Olbrich, Hwang, and Gopalakrishnan with the configuration of Morrison to allow the system to have the same clock frequency determined by the output of the memory buffer from the deserializer output speed and the number of channels output like the claimed invention.
Claim(s) 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Olbrich et al. (US 20160034227 A1) in view of Hwang et al. (US 20050248992 A1), in further view of Uehara (US 20090316494 A1).
Regarding claims 5 and 12: Olbrich discloses a flash storage controller and flash memory (FIG. 3) where in the buffer memory corresponds to static random access memory (SRAM) (each Flash Stage Buffer is an SRAM, par. 92).
Olbrich does not disclose the SRAM having a plurality of bank memories.
Uehara does disclose a semiconductor memory device (FIG 1), where in the SRAM is a buffer memory constituting a plurality of banks (par. 44).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SRAM buffer memory of the system of Olbrich and Hwang with the configuration of Uehara to allow the SRAM buffer to be disclosed of comprising a plurality of banks like the claimed invention.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Olbrich et al. (US 20160034227 A1) in view of Hwang et al. (US 20050248992 A1), in further view of Hsu et al. (US 20190179573 A1).
Regarding claim 16: Olbrich does not disclose a memory system where the external device comprises a field programmable gate array (FPGA).
Hsu discloses a microcontroller architecture for non-volatile memory, wherein the external device comprises a field programmable gate array (FPGA) (the external controller 122 from the memory device can be an FPGA (Field Programmable Gate Array), par. 31).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Olbrich and Hwang with the configuration of Hsu to allow the external device to the memory system be a field programmable gate array like the claimed invention.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Olbrich et al. (US 20160034227 A1) in view of Hwang et al. (US 20050248992 A1), in further view of Uehara (US 20090316494 A1), in further view of Gopalakrishnan et al. (US 20140029331 A1).
Regarding claim 18: Olbrich discloses a flash storage controller and flash memory (FIG. 3) where in the buffer memory corresponds to static random access memory (SRAM) (each Flash Stage Buffer is an SRAM, par. 92).
Olbrich does not disclose the SRAM having a plurality of bank memories.
Uehara does disclose a semiconductor memory device (FIG 1), where in the SRAM is a buffer memory constituting a plurality of banks (par. 44).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SRAM buffer memory of the system of Olbrich and Hwang with the configuration of Uehara to allow the SRAM buffer to be disclosed of comprising a plurality of banks like the claimed invention.
Olbrich, Hwang, and Uehara do not disclose the deserializer is further configured to receive the data from the external device through N channels and to divide the data into M pieces per channel by deserializing the data into NxM channels.
Gopalakrishnan does disclose a memory device with multi-mode deserializer (FIG. 2) configured for serial to parallel data conversion allowing for a number of input channels and a plurality of output channels to match an NxM channel ratio (par. 18 and 25).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the deserializers of the system of Olbrich, Hwang, and Uehara with the configuration of Gopalakrishnan to allow the deserializers to have the channel input and output relationship as the claimed invention.
Allowable Subject Matter
Claims 6-7, 13-14, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: and an additional bank memory among the plurality of bank memories configured to store duration information indicating a time period for each event as in claims 6, 13, and 19; and receive, from the buffer memory, a first piece of duration information and a first piece of data, the first piece of data corresponding to a first event, and repeatedly apply the first piece of data to the nonvolatile memory device for a time period indicated by the first piece of duration information as in claims 7, 14, and 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTHONY THINH TANG/
Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights