Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claims 1-20 are pending.
The IDS, filed 1/8/25, has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, or 4 of U.S. Patent No. 11,237,769.
Claim(s) 1, 2, or 4 of patent #11,237,769 contain(s) every element of claim(s) 1-7 of the instant application and as such anticipate(s) claim(s) 1-7 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is an example mapping between the claim of the current application and patent:
Current Application
A memory system connectable to a host, the memory system comprising: a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation; and a controller electrically connected to the nonvolatile memory and configured to: manage a plurality of block groups, each of the plurality of block groups including one or more of the plurality of blocks, the plurality of block groups including at least a first block group; manage a plurality of logical regions, the plurality of logical regions including at least a first logical region; allocate the first block group to the first logical region for dedicatedly writing data associated with the first logical region;
execute a first operation to the first block group, the first operation including the data erase operation to each of the one or more of the plurality of blocks included in the first block group;
while a period elapsed from the execution of the first operation is shorter than a first threshold, in response to receiving, from the host, one or more first write requests each specifying the first logical region, write first data requested by the one or more first write requests into the first block group; and
when the period elapsed after the execution of the first operation is longer than the first threshold and an unwritten region is included in the first block group, change a state of the first block group such that data not associated with the first logical region is also to be written into the first block group.
Patent 1,237,769
A memory system connectable to a host, comprising: a nonvolatile memory; and a controller electrically connected to the nonvolatile memory and configured to allocate one storage region of a plurality of storage regions included in the nonvolatile memory to each of a plurality of zones to which a plurality of logical address ranges obtained by dividing a logical address space for accessing the memory system are allocated, respectively, wherein the controller is configured to: execute an erase operation for a first storage region allocated to a first zone of the plurality of zones; during a period from the execution of the erase operation for the first storage region until a first time elapses, in response to receiving one or more write requests for specifying the first zone from the host, execute a first write operation including an operation of transferring write data associated with a set of the one or more write requests from a write buffer of the host to an internal buffer of the memory system, and an operation of writing the write data transferred to the internal buffer into the first storage region; when the first time has elapsed after the execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, not execute the first write operation, allocate the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of the plurality of zones; and in response to receiving from the host a first request for causing a state of the first zone or another zone to transition to a state in which writing is suspended, acquire remaining write data of write data associated with one or more received write requests for specifying the first zone or the other zone, from the write buffer of the host, the remaining write data being write data un-transferred to the internal buffer, and write the acquired remaining write data into the unwritten region of the first storage region allocated as the nonvolatile buffer.
4. The memory system of claim 1, wherein the controller is configured to: when a second time longer than the first time has elapsed after the execution of the erase operation for the first storage region, determine whether or not the entire first storage region is filled with data; and when the entire first storage region is not filled with data, set the first storage region to a state in which the entire first storage region is filled with data, by writing dummy data generated by the controller into an unwritten region of the first storage region.
The current claim uses the term “plurality of blocks” while as the patent uses “a plurality of storage regions”. The current claim uses the term “block group” while the patent uses “region”. It would be obvious that the terminologies the current claim uses are interchangeable with those in the patent as they refer to the same things.
Claim 4 (incorporating claim 1) of patent 11,237,769 includes all of the limitations of claim 1 of the instant application, and further limitations, anticipating claim 1 of the instant application.
Dependent claims 2-7 are similarly mapped to claims 1, 2, or 4 of the patent.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 3, 5, or 13 of U.S. Patent No. 11,768,632.
Claim(s) 1, 2, 3, 5, or 13 of patent #11,768,632 contain(s) every element of claim(s) 1-7 of the instant application and as such anticipate(s) claim(s) 1-7 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is an example mapping between the claim of the current application and patent:
Current Application
A memory system connectable to a host, the memory system comprising: a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation; and a controller electrically connected to the nonvolatile memory and configured to: manage a plurality of block groups, each of the plurality of block groups including one or more of the plurality of blocks, the plurality of block groups including at least a first block group; manage a plurality of logical regions, the plurality of logical regions including at least a first logical region; allocate the first block group to the first logical region for dedicatedly writing data associated with the first logical region;
execute a first operation to the first block group, the first operation including the data erase operation to each of the one or more of the plurality of blocks included in the first block group;
while a period elapsed from the execution of the first operation is shorter than a first threshold, in response to receiving, from the host, one or more first write requests each specifying the first logical region, write first data requested by the one or more first write requests into the first block group; and
when the period elapsed after the execution of the first operation is longer than the first threshold and an unwritten region is included in the first block group, change a state of the first block group such that data not associated with the first logical region is also to be written into the first block group.
Patent 11,768,632
1. A memory system connectable to a host including a first memory, the memory system comprising: a nonvolatile memory; a second memory; and a controller electrically connected to the nonvolatile memory and configured to allocate one storage region of a plurality of storage regions included in the nonvolatile memory to each of a plurality of zones to which a plurality of logical address ranges obtained by dividing a logical address space for accessing the memory system are allocated, respectively, wherein the controller is configured to: execute an erase operation for a first storage region allocated to a first zone of the plurality of zones; during a period from the execution of the erase operation for the first storage region until a first time elapses, in response to receiving one or more write requests for specifying the first zone from the host,
execute a first write operation including an operation of transferring write data associated with the one or more write requests from the first memory of the host to the second memory, and an operation of writing the write data transferred to the second memo into the first storage region; when the first time has elapsed after the execution of the erase operation and an unwritten region in the first storage region has a size larger than or equal to a first size, allocate the first storage region as a nonvolatile buffer for storing write data to be written to each of the plurality of zones; and
in response to receiving from the host a first request for causing a state of the first zone or another zone to transition to a state in which writing is suspended, acquire first write data of write data associated with one or more received write requests for specifying the first zone or the other zone, from the first memory of the host, the first write data being un-transferred to the second memory, and write the acquired first write data into the unwritten region of the first storage region allocated as the nonvolatile buffer.
5. The memory system of claim 1, wherein the controller is configured to: when a second time longer than the first time has elapsed after the execution of the erase operation for the first storage region, determine whether or not there is an unwritten region in the first storage region; and when there is the unwritten region in the first storage region, write dummy data generated by the controller into the unwritten region of the first storage region.
From the above claim mapping, it is clear that claim 5 (incorporating claim 1) of the patent includes all of the limitations of claim 1 of the instant application, and further limitations, anticipating claim 1 of the instant application.
Dependent claims 2-7 are similarly mapped to claims 1, 2, 3, or 5 of the patent.
Claims 1-7 and 10-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5, 13, 15, 17, or 19 of U.S. Patent No. 12,229,448.
Claim(s) 1, 3, 5, 13, 15, 17, or 19 of patent #11,768,632 contain(s) every element of claim(s) 1-7 of the instant application and as such anticipate(s) claim(s) 1-7 and 10-17 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is an example mapping between the claim of the current application and patent:
Current Application
A memory system connectable to a host, the memory system comprising: a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation; and a controller electrically connected to the nonvolatile memory and configured to: manage a plurality of block groups, each of the plurality of block groups including one or more of the plurality of blocks, the plurality of block groups including at least a first block group; manage a plurality of logical regions, the plurality of logical regions including at least a first logical region; allocate the first block group to the first logical region for dedicatedly writing data associated with the first logical region;
execute a first operation to the first block group, the first operation including the data erase operation to each of the one or more of the plurality of blocks included in the first block group;
while a period elapsed from the execution of the first operation is shorter than a first threshold, in response to receiving, from the host, one or more first write requests each specifying the first logical region, write first data requested by the one or more first write requests into the first block group; and
when the period elapsed after the execution of the first operation is longer than the first threshold and an unwritten region is included in the first block group, change a state of the first block group such that data not associated with the first logical region is also to be written into the first block group.
Patent 12,229,448
A memory system connectable to a host including a first memory, the memory system comprising: a nonvolatile memory; a second memory; and a controller configured to allocate one storage region of a plurality of storage regions included in the nonvolatile memory to each of a plurality of logical regions, wherein the controller is further configured to: execute an erase operation for a first storage region allocated to a first logical region of the plurality of logical regions; during a period from the execution of the erase operation for the first storage region until a first time elapses, in response to receiving one or more write requests for specifying the first logical region from the host,
execute a first write operation including an operation of transferring write data associated with the one or more write requests from the first memory of the host to the second memory, and an operation of writing the write data transferred to the second memory into the first storage region; when the first time has elapsed after the execution of the erase operation and an unwritten region in the first storage region has a size larger than or equal to a first size, allocate the first storage region as a nonvolatile buffer for storing write data to be written to each of the plurality of logical regions; and when the first time has elapsed after the execution of the erase operation and the unwritten region in the first storage region has a size smaller than the first size, continue to execute the first write operation.
5. The memory system of claim 1, wherein the controller is further configured to: when a second time longer than the first time has elapsed after the execution of the erase operation for the first storage region, determine whether or not there is an unwritten region in the first storage region; and when there is the unwritten region in the first storage region, write dummy data generated by the controller into the unwritten region of the first storage region.
From the above claim mapping, it is clear that claim 5 (incorporating claim 1) of the patent includes all of the limitations of claim 1 of the instant application, and further limitations, anticipating claim 1 of the instant application.
Independent claim 11 is similarly mapped to claim 19 (incorporating claim 13) of the patent.
Dependent claims 2-7, 11-17 are similarly mapped to claims 1, 2, 3, 5, 13, 15, 17, or 19 of the patent.
Allowable Subject Matter
Claims 8-9 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and by submission of a terminal disclaimer to overcome the double patenting rejection set forth in this office action.
As to claim 8/18, the prior art does not further suggest the memory system of claim 1/11, wherein the controller is further configured to determine the first threshold based on at least one of the number of first operations executed to the first block group, a bit error rate of the first block group, the number of program errors of the first block group, or the number of erase errors of the first block group.
As to claim 9/19, the prior art does not further suggest the memory system of claim 1/11, wherein each of the plurality of block groups includes only one of the plurality of blocks.
As to claim 20, the prior art does not further suggest the method of claim 11, wherein each of the plurality of logical regions is a zone defined in the NVM Express standard.
Similar prior art (US 20100049913) teaches a storage device with a controller configured to managing access to logical blocks, in response to receiving a first command set, execute a first erase operation which is included in an erase operation of data of the first memory cell, and suspend the first erase operation, and in response to receiving a second command set, execute a read operation or a write operation of the second memory cell and subsequently resume the suspended first erase operation. The prior art does not discloses while a period elapsed from the execution of the first operation is shorter than a first threshold, in response to receiving, from the host, one or more first write requests each specifying the first logical region, write first data requested by the one or more first write requests into the first block group; and when the period elapsed after the execution of the first operation is longer than the first threshold and an unwritten region is included in the first block group, change a state of the first block group such that data not associated with the first logical region is also to be written into the first block group.
Another prior art (US20180314444) teaches a memory device having a first and second storage areas corresponding to a writing unit, writing first data into one or more unwritten second areas of the first area and writing second data into unwritten second areas of the first area. This art is silent as to teaching the reasons for allowance disclosed above.
Another prior art (US20160321171) teaches garbage collection and using a write buffer memory WB for 13. WB temporarily stores write data received from the information processing devices and a garbage collection buffer memory GB for temporarily stores data (valid data) in garbage collection described later. The write buffer memory WB temporarily stores the write data until it reaches to a predetermined data size suitable for the nonvolatile memory. This art is silent as to teaching the reasons for allowance disclosed above.
Conclusion
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/THAN NGUYEN/Primary Examiner, Art Unit 2138