DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/8/2025 was considered by the examiner.
Drawings
The drawings received on 1/8/2025 have been accepted by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 3, the claimed program speed is indefinite because it is unclear how the program speed is being measured, what program is the speed being measured for, or what value of the program speed is a deciding factor. These deficiencies are not clarified by the specification. Clarification of this term is required.
Claim 3, the claimed program speed being determined based on an oxide thickness is unclear since it is not clearly defined how the oxide thickness relates to the speed. The lack of relationship between these characteristics renders the claim indefinite.
Claims 1, 4-7, 14-21; the limitations drawn to an access number and access time render the claims indefinite since it is not clear how these are being tracked, what these values truly represent, how they are being used to map. Clarification is required.
Claims 4-7 and 16-18; the claimed ranking renders these claims indefinite since it is not clear what the ranking logic involves, how it interacts with the previously disclosed grouping and how the access number and access time are involved. Clarification is required.
Claim 11, the claimed limit value has not been properly defined and therefore, it is not clear how this value is chosen, where it comes from or how its used. Clarification is required.
All other dependent claims not independently rejected are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for having the same deficiencies as their corresponding parent claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-21 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang [US 10,409,526] in view of Luo et al. [US 11,488,670].
Claim 1, Zhang discloses a memory system [Fig 1] comprising: a memory device including a plurality of sequential areas in which data corresponding to consecutive logical addresses [flash memory 20] received from a host device [user 5] are stored; and a memory controller [processor 15] configured to receive, from the host device, a write request including the data and the logical addresses [Col. 1, line 62 – Col. 2, line 22], to group the plurality of sequential areas into a plurality of sequential area groups based on a value corresponding to each of the plurality of sequential areas [consolidating hot and cold blocks, Abstract, based on a heuristic parameter, Col 4, lines 21-35] and to map each of the logical addresses to one of the plurality of sequential area groups based on an access number [heat determined based on frequency, Col. 13, lines 28-38], and an access time of the data [heat property based on time, Col. 13, lines 28-38]. Zhang does not teach but Luo et al discloses grouping based on program speed [combined together to form a storage volume based on different parameters including speed, see Col. 2, lines 55-66]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the hot/cold grouping of Zhang with the speed aware grouping of Lue et al. since doing so optimizes system performance by mapping hot data to areas with faster speeds to minimize latency.
Claim 2, Zhang in view of Luo et al. discloses the memory system of claim 1, wherein the plurality of sequential area groups includes a hot group, a warm group, and a cold group [abstract], and wherein the memory controller groups a first quantity of sequential areas as the hot group in an order in which the program speed is highest among the plurality of sequential areas, groups a second quantity of sequential areas as the cold group in an order in which the program speed is lowest among the plurality of sequential areas, and groups as the warm group other sequential areas, among the plurality of sequential areas, that are not included in the hot group or the cold group [hot/cold ranking, Col. 14, lines 14-67].
Claim 3, Zhang in view of Luo et al. discloses the memory system of claim 1, wherein the memory device includes memory cells stacked in a three-dimensional structure, and wherein the program speed is determined based on a thickness of an oxide in which the memory cells are stacked [Luo Col. 2, lines 26-54].
Claim 4, Zhang in view of Luo et al. discloses the memory system of claim 2, wherein the memory controller stores logical addresses in a buffer in an order in which the logical addresses are received from the host device, and performs a re-ordering operation including determining a ranking of each of the logical addresses stored in the buffer based on the access number and the access time [Col. 7, lines 20-30].
Claim 5, Zhang in view of Luo et al. discloses the memory system of claim 4, wherein the memory controller determines the ranking for each of the logical addresses in an order in which the access number having a highest value is assigned a highest ranking [Col. 14, lines 14-67].
Claim 6, Zhang in view of Luo et al. discloses the memory system of claim 5, wherein the memory controller determines the ranking for each logical address among logical addresses having a same access number in an order in which the logical address last received from the host device is assigned a highest ranking [Col. 14, lines 14-67].
Claim 7, Zhang in view of Luo et al. discloses the memory system of claim 4, wherein the memory controller maps a first quantity of logical addresses to the hot group in an order in which the ranking is highest among the re-ordered logical addresses, maps a second quantity of logical addresses to the cold group in an order in which the ranking is lowest among the re-ordered logical addresses, and maps to the warm group other logical addresses not included in the hot group or the cold group [Col. 6, line 54 – Col. 7, line 10 and Col. 14, line 14-67].
Claim 8, Zhang in view of Luo et al. discloses the memory system of claim 1, wherein the memory controller controls the memory device to perform a write operation corresponding to the write request based on the logical addresses mapped to the plurality of sequential area groups [Col. 6, lines 50-65].
Claim 9, Zhang in view of Luo et al. discloses the memory system of claim 4, wherein the memory controller performs the re-ordering operation based on whether an enable signal for the re-ordering operation is received [Col. 8, lines 46-65].
Claim 10, Zhang in view of Luo et al. discloses the memory system of claim 4, wherein the memory controller performs the re-ordering operation based on a size of the data [consolidating hot and cold blocks, Abstract, based on a heuristic parameter which may be interpreted as size, Col 4, lines 21-35].
Claim 11, Zhang in view of Luo et al. discloses the memory system of claim 10, wherein the memory controller maps logical addresses to the hot group when size of the data is smaller than a first limit value and maps logical addresses to the cold group when size of the data is greater than a second limit value greater than the first limit value [consolidating hot and cold blocks, Abstract, based on a heuristic parameter which may be interpreted as size, Col 4, lines 21-35].
Claim 12, Zhang in view of Luo et al. discloses the memory system of claim 4, wherein the memory controller performs the re-ordering operation based on a characteristic of the data [Col. 7, line 35-40].
Claim 13, Zhang in view of Luo et al. discloses the memory system of claim 12, wherein the memory controller maps logical addresses based on whether the data is journal data, map data, or firmware data [Col. 7, lines 35-40].
Claims 14-21 are rejected using the same rationale as Claims 1-14 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Klosterman et al. [US 2022/0321567]; Context Tracking Across a Data Management Platform. See par. 0154.
Fisher et al. [US 9,928,166]; Detecting Hot Spots Through Flash Memory Management Table Snapshots. See Claims 1, 5, 9.
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/MIDYS ROJAS/ Primary Examiner, Art Unit 2133