DETAILED ACTION
Claims 1-20 are pending in this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/24/2025, 2/4/2025, 3/4/2025, 7/23/2025, 9/5/2025 and 6/23/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8-11 and 15-17 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Jejurikar et al. (US PGPUB No. 2015/0095662) [hereinafter “Jejurikar”].
As per claim 1, Jejurikar teaches a device, comprising: a plurality of memory regions (Abstract, allocating different memory regions); and a processor configured to execute a plurality of groups of instructions ([0035], processors for executing instructions) see also ([0009], tables with known instructions built for execution by processor), wherein the groups of instructions are configured to be in a plurality of domains for execution in the processor ([0035], processors for executing instructions for different domains); wherein the device is configured to, during execution of a first instruction in the processor to load a second instruction from a memory region among the plurality of memory regions ([0035], processors execute instructions for one of the domains): determine a first domain, among the plurality of domains, for the execution of the first instruction in the processor ([0035], processors execute application instructions from different regions, i.e. App A domain and App B domain); determine whether a second domain, among the plurality of domains, for execution of the second instruction in the processor is same as the first domain ([0035] and [0036], processor and memory controller determine which domain is being accessed and multiple domains may be executed at the same time, i.e. App A domain and App B domain); and determine, based on a permission setting, whether to provide access to the memory region to load the second instruction in response to a determination that the second domain is different from the first domain ([0036], processor and memory controller determines a different domain and checking access policy of the domain).
As per claim 2, Jejurikar teaches the device of claim 1, wherein the first domain is determined based on the first instruction being in a first group of instructions configured in the first domain ([0004], identifying commands and request made by specific domains); and the second domain is determined based on the second instruction being in a second group of instructions configured in the second domain see id.
As per claim 3, Jejurikar teaches the device of claim 2, wherein the processor includes a register configured to store data indicative of a respective domain of a respective instruction being currently executed in the processor (Claim 21, registers storing domain-specific keys of current domains).
As per claim 4, Jejurikar teaches the device of claim 3, wherein the respective domain is determined based on the respective instruction being part of a respective group of instructions configured in the respective domain (Abstract and [0004], requests made with domain-specific keys are configured instructions specifically for an application).
As per claim 8, the substance of the claimed invention is identical or substantially similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
As per claim 9, the substance of the claimed invention is identical or substantially similar to that of claim 2. Accordingly, this claim is rejected under the same rationale.
As per claim 10, the substance of the claimed invention is identical or substantially similar to that of claim 3. Accordingly, this claim is rejected under the same rationale.
As per claim 11, the substance of the claimed invention is identical or substantially similar to that of claim 4. Accordingly, this claim is rejected under the same rationale.
As per claim 15, the substance of the claimed invention is identical or substantially similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
As per claim 16, the substance of the claimed invention is identical or substantially similar to that of claim 2. Accordingly, this claim is rejected under the same rationale.
As per claim 17, the substance of the claimed invention is identical or substantially similar to that of claims 3 and 4. Accordingly, this claim is rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-7, 12-14 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jejurikar in view of Epstein (US PGPUB No. 2013/0086299).
As per claim 5, Jejurikar teaches the device of claim 4.
Jejurikar does not explicitly teach wherein the plurality of domains include: instructions of hypervisor; instructions of operating system; and instructions of applications. Epstein teaches wherein the plurality of domains include: instructions of hypervisor; instructions of operating system; and instructions of applications (Abstract and [0189], allocating page tables for hypervisor and operating system to memory which include instructions).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Jejurikar with the teachings of Epstein, wherein the plurality of domains include: instructions of hypervisor; instructions of operating system; and instructions of applications, to apply the security and efficiency of dedicated memory regions to all well known software components.
As per claim 6, the combination of Jejurikar and Epstein teaches the device of claim 5, wherein the permission setting is configured in a table entry used to compute a physical memory address in the memory region from a virtual memory address used in the execution of the first instruction ([0049], generating page tables that may virtual-to-physical memory address for instructions that can be domain-specific see [0050]).
As per claim 7, the combination of Jejurikar and Epstein teaches the device of claim 6, wherein the table entry includes a plurality of permission settings for the plurality of domains respectively ([0050]-[0051], access control settings for a plurality of domains including shared memory) and a base for computing the physical memory address from the virtual memory address ([0048], MMU uses page translations for computing physical address from virtual address, i.e. base); and wherein the permission setting pre-associated with the second domain ([0050], each domain has domain keys to access associated memory pages).
As per claim 12, the substance of the claimed invention is identical or substantially similar to that of claim 5. Accordingly, this claim is rejected under the same rationale.
As per claim 13, the substance of the claimed invention is identical or substantially similar to that of claim 6. Accordingly, this claim is rejected under the same rationale.
As per claim 14, the substance of the claimed invention is identical or substantially similar to that of claim 7. Accordingly, this claim is rejected under the same rationale.
As per claim 18, the substance of the claimed invention is identical or substantially similar to that of claim 5. Accordingly, this claim is rejected under the same rationale.
As per claim 19, the substance of the claimed invention is identical or substantially similar to that of claim 6. Accordingly, this claim is rejected under the same rationale.
As per claim 20, the substance of the claimed invention is identical or substantially similar to that of claim 7. Accordingly, this claim is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dinechin et al. (US PGPUB No. 2006/0036830), Koufaty et al. (US PGPUB No. 2016/0350019), Guim et al. (US PGPUB No. 2017/0286326), Jin et al. ("Architectural support for secure virtualization under a vulnerable hypervisor," 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, 2011, pp. 272-283), Jin et al. ("Secure MMU: Architectural support for memory isolation among virtual machines," 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W), Hong Kong, China, 2011, pp. 217-222, doi: 10.1109/DSNW.2011.5958816), Sousa et al. ("HSP-V: Hypervisor-Less Static Partitioning for RISC-V COTS Platforms," in IEEE Access, vol. 12, pp. 71131-71144, 2024, doi: 10.1109/ACCESS.2024.3399601) and Sundaravarathan et al. ("Controlled Shared Memory (COSM) Isolation: Design and Testbed Evaluation," in IEEE Access, vol. 13, pp. 77893-77917, 2025, doi: 10.1109/ACCESS.2025.3564391) all disclose various aspects of the claimed invention including dedicated memory regions for different domains to be executed by a processor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER C SHAW whose telephone number is (571)270-7179. The examiner can normally be reached Max Flex.
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/PETER C SHAW/Primary Examiner, Art Unit 2493 July 16, 2026
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