DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 11,171,658) in view of Tseng et al. (US 10,044,357, hereinafter “Tseng”).
With respect to Claim 9, Nakamura teaches
a phase-locked loop circuit configured to restore a clock signal based on a signal received from an external device (Nakamura: Col. 2, lines 49-57, Col. 3, lines 3-12, a PLL implemented within an electronic device containing an interface circuit for external connections. Secondary teachings of Tseng, at Col. 2, lines 31-47, expressly disclose that such clock and data recovery (CDR) circuits are used in display drivers to process image data.); and
wherein the phase-locked loop circuit includes:
a voltage-controlled oscillator configured to output a variable clock signal with an oscillation frequency based on a control voltage (Nakamura: Abstract, Col. 3, lines 19-33, Fig. 2, the PLL including a voltage-controlled oscillator VCO 10 and a calibration circuit (bandwidth selection circuit)); and
a bandwidth selection circuit configured to output a binary code value supplied to the voltage-controlled oscillator (Nakamura: Abstract, Col. 2, lines 4-22, Col. 3, line 52 – Col. 4, line 3, the calibration circuit (CAL) configured to generate a code based on the frequency comparison of the reference and clock signals), and
wherein the voltage-controlled oscillator generates the restored clock signal by outputting the variable clock signal based on a bandwidth selected according to the binary code value (Nakamura: Col. 3, lines 19-33, Col. 6, lines 29-40, the VCO changes its base oscillation frequency by receiving the calibration code. Under the Broadest Reasonable Interpretation (BRI), choosing a base oscillation frequency to broaden the operating range is functionally equivalent to selecting a bandwidth interval.).
While Nakamura teaches, at Col. 2, lines 49-57, an electronic device with a controller and an interface circuit for host connections, however, fails to expressly disclose a display driver comprising control logic to process image data.
However, Tseng discloses:
a display driver (Tseng: Col. 1, line 4-25), and
a control logic circuit configured to process image data using the restored clock signal (Tseng: Col. 2, lines 31-47, a display driver comprising a PLL for clock restoration).
Therefore, it would be obvious to one of ordinary skill in the art to implement the automated selection circuit of Nakamura within the display driver system of Tseng in order to achieve the taught benefit of optimized initial control voltage and faster locking (Tseng: Col. 2, lines 31-55).
Apparatus claim (1) is drawn to the substantially analogous apparatus (with the exception of the frame of reference of the display driver as the intended use for the PLL) as claimed in claim (9). Therefore, apparatus claim (1) corresponds to apparatus claim (9), and is rejected for the same reasons of obviousness as used above.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura and Tseng, and further in view of Rogers et al. (US 2019/0207610, hereinafter “Rogers”).
With respect to Claim 10, the combination of Nakamura as modified by Tseng teaches the display driver of claim 9, wherein the input signal of the phase-locked loop circuit includes a reference clock signal (Nakamura: Col. 3, lines 3-18, receiving a reference clock signal (REFCLK) via node REFCLKIN).
Nakamura and Tseng fails to expressly disclose:
the bandwidth selection circuit includes a delay-locked loop circuit configured to lock an internal clock signal at the same frequency as the reference clock signal using the reference clock signal and to output two clock signals having a 1 unit interval (UI) phase difference.
However, Rogers discloses:
the bandwidth selection circuit includes a delay-locked loop circuit (Rogers: Para. [0014], a feedback portion of a PLL includes a delay locked loop (DLL)) configured to lock an internal clock signal at the same frequency as the reference clock signal using the reference clock signal and to output two clock signals having a 1 unit interval (UI) phase difference (Rogers: Para. [0006], [0045], claim 6, using a shift register to generate indicator signals where a “first indication signal is one clock cycle ahead of the second”).
Therefore, it would be obvious to one of ordinary skill in the art to modify the calibration circuit, as taught by Nakamura, to incorporate the DLL-based 1UI timing, as taught by Rogers, in order to improve clock granularity (Rogers: Para. [0004], [0030], [0049]).
Apparatus claim (2) is drawn to the substantially analogous apparatus as claimed in claim (10). Therefore, apparatus claim (2) corresponds to apparatus claim (10), and is rejected for the same reasons of obviousness as used above.
Claims 3-8 and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura, Tseng and Rogers, and further in view of Sjoland et al. (US 2019/0131978, hereinafter “Sjoland”).
With respect to Claim 11, the combination of Nakamura as modified by Tseng and Rogers teaches the display driver of claim 10.
Nakamura, Tseng and Rogers fail to expressly disclose:
wherein the binary code value is determined based on the two clock signals.
However, Sjoland discloses:
wherein the binary code value is determined based on the two clock signals (Sjoland: Para. [0041] – [0042], discloses a process where a digital control word is generated based on a comparison between reference and feedback signals).
Therefore, it would be obvious to one of ordinary skill in the art to further modify the calibration circuit, as taught by Nakamura, to incorporate the delayed-replica comparison and digital conversion logic, as taught by Sjoland, in order to improve sequence optimization (Sjoland: [0059], [0082]).
With respect to Claim 12, the combination of Nakamura as modified by Tseng, Rogers and Sjoland teaches the display driver of claim 11, wherein the two clock signals include a first clock signal and a second clock signal, and
the first clock signal leads the second clock signal in phase (Rogers: Para. [0045], the first signal is ahead of the second in phase).
With respect to Claim 13, the combination of Nakamura as modified by Tseng, Rogers and Sjoland teaches the display driver of claim 12, wherein:
the bandwidth selection circuit further includes a multi-band selector, and
the multi-band selector is configured to:
receive the two clock signals,
divide a predetermined frequency band into a plurality of intervals and assign delay times to each interval (Sjoland: Para. [0041] – [0042], a frequency divider providing a first feedback signal and a second feedback signal where the second is a replica delayed with respect to the first), and
determine the binary code value by comparing a delay clock signal, generated by applying the interval-specific delay time to the first clock signal, with the second clock signal (Sjoland: Para. [0083], generating phase delay signals based on a comparison between the respective feedback signals to generate the control word).
With respect to Claim 14, the combination of Nakamura as modified by Tseng, Rogers and Sjoland teaches the display driver of claim 13, wherein the number of the plurality of intervals is 2 raised to the power of n, where n is a natural number (Nakamura, Fig. 4-5, Col. 5, lines 8-31, calibration codes (4-bit) which define 2 raised to the power of n (16) intervals), and
the interval-specific delay times are sequentially configured as multiples of the shortest delay time among the interval-specific delay times (Sjoland: Claim 4, Para. [0082], the delay in the feedback path is an “integer multiple of the half-period of the oscillator signal”).
With respect to Claim 15, the combination of Nakamura as modified by Tseng, Rogers and Sjoland teaches the display driver of claim 13, wherein the multi-band selector is configured to:
determine, for each interval, whether the delay clock signal lags behind the second clock signal in phase (Sjoland: Para. [0064], the reference signal precedes delayed feedback signal FBD and lags the feedback signal),
generate a thermometer code value based on the determination result, and
convert the thermometer code value into the binary code value (Sjoland: Para. [0074], Fig. 5, an oscillator with a binary-to-thermometer decoder 21. The user of thermometer-to-binary (T2B) conversion logic to interface comparison results with a digitally-coded oscillator is standard digital logic for these architectures).
With respect to Claim 16, the combination of Nakamura as modified by Tseng, Rogers and Sjoland teaches the display driver of claim 15, wherein the multi-band selector is configured to determine, for each interval, that a output signal of a frequency comparator is output as a low-level signal(0) if the phase of the delay clock signal leads that of the second clock signal, and the multi-band selector determines for each interval that the output signal of the frequency comparator is output as a high-level signal(1) if the phase of the delay clock signal lags behind that of the second clock signal (Rogers: Para. [0044], Fig. 3A, timing diagrams where edge occurrences of the two phase-shifted signals are denoted as “0” and “1” on the clock waveform to indicate their relative phase relationship).
Apparatus claims (3, 4, 5, 6, 7 & 8) are drawn to the substantially analogous apparatus as claimed in claims (11, 12, 13, 14, 15 & 16). Therefore, apparatus claims (3, 4, 5, 6, 7 & 8) correspond to apparatus claims (11, 12, 13, 14, 15 & 16), and are rejected for the same reasons of obviousness as used above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/BRYAN EARLES/Primary Examiner, Art Unit 2625