Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 28 March 2025.
ALLOWABLE SUBJECT MATTER
Claims 2-21 indicated allowable over the cited prior art.
REJECTIONS NOT BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 2-21 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, and 19 of U.S. Patent No. 12223184.
19/013982, Claim 2
12223184, Claim 6
A memory system, comprising:
a set of memory devices; and
processing circuitry coupled with the set of memory devices and configured to cause the memory system to:
A memory system, comprising:
a set of memory devices; and
processing circuitry coupled with the set of memory devices and configured to cause the memory system to:
receive a command to initialize the set of memory devices included in the memory system;
receive, from a host system, a command to initialize the set of memory devices included in the memory system;
select, in accordance with the command, a first memory device from the set of memory devices in accordance with a randomly selected number;
select, based at least in part on the command, a first memory device from the set of memory devices using an output of a random number generator;
perform a first initialization procedure corresponding to the command on a first subset of the set of memory devices according to a first operational parameter corresponding to the first memory device, the first subset of the set of memory devices comprising the first memory device; and
perform a first initialization corresponding to the command on a first subset of the set of memory devices according to the first operational parameter, the first subset of the set of memory devices comprising the first memory device;
store, at one or more registers, a first result associated with performance of the first initialization procedure, wherein the first result comprises a successful result or a failed result.
store the first result and the second result in one or more registers.
Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the present application are broader than and encompass the subject matter of the claims from the patent. The dependent claims recite intermediate limitations that correspond in scope to limitations recited in claim 6 of the patent, namely with respect to reading operational parameters, and performing subsequent initialization.
19/013982, Claim 11
12223184, Claim 1
A memory system, comprising:
a set of memory devices; and
processing circuitry coupled with the set of memory devices and configured to cause the memory system to:
A memory system, comprising:
a set of memory devices; and
processing circuitry coupled with the set of memory devices and configured to cause the memory system to:
receive a command to initialize the set of memory devices included in the memory system;
receive, from a host system, a command to initialize the set of memory devices included in the memory system;
select, in accordance with the command, a first memory device from the set of memory devices in accordance with a randomly selected number;
select, based at least in part on the command, a first memory device from the set of memory devices using an output of a random number generator;
perform a first initialization procedure, corresponding to the command, on a first subset of the set of memory devices according to a first operational parameter that corresponds to the first memory device, wherein the first subset of the set of memory devices comprises the first memory device; and
perform a first initialization corresponding to the command on a first subset of the set of memory devices according to the first operational parameter, the first subset of the set of memory devices comprising the first memory device;
perform, in accordance with performing the first initialization procedure, a second initialization procedure, corresponding to the command, on a second subset of the set of memory devices according to a set of second operational parameters,
perform, after performing the first initialization and reading the set of second operational parameters, a second initialization corresponding to the command on the second subset of the set of memory devices according to the set of second operational parameters; and
wherein each second operational parameter of the set of second operational parameters corresponds to a respective memory device of the second subset of the set of memory devices, the second subset of the set of memory devices different than the first subset of the set of memory devices.
read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of a second subset of the set of memory devices different than the first subset of the set of memory devices;
Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the present application are broader than and encompass the subject matter of the claims from the patent. The dependent claims recite intermediate limitations that correspond in scope to limitations recited in claim 6 of the patent, namely with respect to reading operational parameters, performing subsequent initialization, and storing results.
19/013982, Claim 21
12223184, Claim 19
A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a memory system, cause the memory system to:
A non-transitory computer-readable medium storing. code comprising instructions which, when executed by processing circuitry of a memory system, cause the memory system to:
receive a command to initialize a set of memory devices included in the memory system;
receive, from a host system, a command to initialize a set of memory devices included in the memory system;
select, in accordance with the command, a first memory device from the set of memory devices in accordance with a randomly selected number;
select, based at least in part on the command, a first memory device from the set of memory devices using an output of a random number generator;
perform a first initialization procedure corresponding to the command on a first subset of the set of memory devices according to a first operational parameter corresponding to the first memory device, the first subset of the set of memory devices comprising the first memory device; and
perform a first initialization corresponding to the command on a first subset of the set of memory devices according to the first operational parameter, the first subset of the set of memory devices comprising the first memory device;
store a first result associated with performance of the first initialization procedure at one or more registries, wherein the first result is a successful result or a failed result.
store the first result and the second result in one or more registers.
Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the present application are broader than and encompass the subject matter of the claims from the patent.
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 20200066364, [0038]: “…Accessing a memory device can include having an ability to perform operations on the memory device and receive results or can include receiving results of previously performed operations. For example, the access can be access through a controller of a memory system which allows the processing device to select individual die on which to perform endurance testing….:
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137