DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action has been issued in response to amendments filed 22 June 2026.
Claims 1 – 3, 5 – 10 and 12 – 20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 5 – 10 and 12 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeh (US 20140372668).
Regarding claim 1, Yeh teaches
A system comprising:
a memory device; (memory device = Fig. 4 non-volatile memory module 106)
and a processing device (processing device = Fig. 4 memory controller 104), operatively coupled with the memory device, to perform operations comprising: (Yeh teaches memory controller 104 performing operations on nvm module 106 (see ¶[41]))
determining that a write request (write request = first logical page of LBA(2) to be updated with updated data UD3) references a partially aligned translation unit (partially aligned translation unit = LBA(2)) by determining that an ending address specified by the write request does not corresponding to an ending address of the partially aligned translation unit; (Examiner is interpreting “partially aligned translation unit” to refer to translation unit that can be partially written to (see spec Fig. 3 TU 0 partially written).) (Yeh teaches determining that first logical page of LBA(2) (partially aligned translation unit) is to be updated with updated data UD3 (see Fig. 11, ¶[73]), wherein said LBA(2) is configured/predefined with 3 logical pages (see Fig. 11, ¶[63]). Note that only a portion (partially) (namely said first logical page) of said LBA(2) is written to. Further note that in Fig. 11, said first logical page is in middle of LBA(2) (partially aligned translation unit) and not at second logical page (ending address) of LBA(2). Further note that said first logical page of LBA(2) is also one and only (i.e. first and last) update to LBA(2). Therefore, said first logical page of LBA(2) is also ending address (ending logical address).)
identifying a first entry in a translation map (translation map = logical-to-physical address mapping table + global random area searching table 800), wherein the first entry identifies a first physical block (first physical block = Fig. 11 physical erasing unit 410(2)) of the memory device, wherein the first physical block is mapped to the partially aligned translation unit; (Yeh teaches recording, in logical-to-physical address mapping table, relationship between logical units LBA(0)-LBA(4) and physical erasing units 410(0)-410(4) (see Fig. 8, ¶[70]) wherein said physical erasing units 410(0)-410(4) are in non-volatile memory 106 (memory device) (see Fig. 4, ¶[42]). Note that there is a first mapping (first entry) between LBA(2) (partially aligned translation unit) and physical erasing unit 410(2) (first physical block).)
creating a second entry in the translation map (translation map = logical-to-physical address mapping table + global random area searching table 800), wherein the second entry identifies a second physical block (second physical block = physical erasing unit 410(5)) of the memory device, wherein the second physical block is mapped to the partially aligned translation unit;
linking, in the translation map, the first entry and the second entry; (Yeh teaches building, in global random area search table 800, root unit 810(2) (second entry) (see ¶[77]) with an entry that maps (mapped) said first logical page of LBA(2) (partially aligned translation unit) (or LBA(2)-1) to second physical programming unit of physical erasing unit 410(5) (second physical block) (or 410(5)-2) (see Fig. 15, ¶[84]) wherein said physical erasing unit 410(5) is in non-volatile memory (memory device) 106 (see Fig. 4, ¶[42]). Note that LBA(2)-1 includes LBA(2) which is also in said first mapping (first entry) between LBA(2) and physical erasing unit 410(2). In other words, LBA(2) links (linking) said root unit 810(2) (second entry) with said first mapping (first entry).)
writing a subset of data corresponding to the partially aligned translation unit to a first portion to the second physical block (Yeh teaches if first logical page of LBA(2) (partially aligned translation units) is to be updated with updated data UD3 (subset of data), issuing programming command to write said UD3 to said second physical programming unit (first portion) of said physical erasing unit 410(5) (second physical block) (see Fig. 11, ¶[73]).)
Claim 8 is the method claim corresponding to system claim 1 and is rejected on the same grounds as claim 1.
Claim 15 is the non-transitory computer-readable storage medium claim corresponding to system claim 1 and is rejected on the same grounds as claim 1. Yeh also teaches
A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device processing device = Fig. 4 memory controller 104), cause the processing device to: (Yeh teaches memory controller 104 includes memory management circuit (see ¶[46]) that includes a microprocessor that executes control instructions in ROM (see ¶[48]).)
Regarding claim 2, Yeh teaches the system of claim 1 where Yeh also teaches
wherein the partially aligned translation unit comprises a predefined number of logical pages and represents a base granularity of data managed by the memory device (Yeh teaches LBA(2) (partially aligned translation unit) configured/predefined with logical pages (see ¶[63]) where Fig. 11 discloses an embodiment of 3 logical pages (predefined number of logical pages) for LBA(2). Yeh also teaches that said logical pages are mapped to physical programming units of physical erasing unit (see Fig. 8, ¶[70]) (in nvm module 106 (memory device) (see Fig. 4)) wherein physical programming unit is minimum unit (base granularity) for writing data (see ¶[43]).)
Claim 9 is the method claim corresponding to system claim 2 and is rejected on the same grounds as claim 2.
Claim 16 is the non-transitory computer-readable storage medium claim corresponding to system claim 2 and is rejected on the same grounds as claim 2.
Regarding claim 3, Yeh teaches the system of claim 1 where Yeh also teaches
wherein determining that the write request references the partially aligned translation unit further comprises:
determining that a starting logical address specified by the write request (write request = first logical page of LBA(2) to be updated with updated data UD3) does not correspond to a starting address of the partially aligned translation unit (Yeh teaches determining that first logical page (starting address) of LBA(2) is to be updated with updated data UD3 (see Fig. 11, ¶[73]). Note that in Fig. 11, said first logical page is in middle of LBA(2) (partially aligned translation unit) and not at zeroth logical page (starting address) of LBA(2).)
Claim 10 is the method claim corresponding to system claim 3 and is rejected on the same grounds as claim 3.
Claim 17 is the non-transitory computer-readable storage medium claim corresponding to system claim 3 and is rejected on the same grounds as claim 3.
Regarding claim 5, Yeh teaches the system of claim 1 where Yeh also teaches
wherein the partially aligned translation unit is a last element of a set of translation units specified by the write request (write request = first logical page of LBA(2) to be updated with updated data UD3) (Examiner is interpreting “set of translation units” to be set of “1”.) (Yeh teaches determining that first logical page of LBA(2) (partially aligned translation unit) is to be updated with updated data UD3 (see Fig. 11, ¶[73]). Note that in Fig. 11, LBA(2) is one and only (i.e. first and last) block (set of translation units) to be updated. Therefore, LBA(2) is also last block (last element) to be updated.)
Claim 12 is the method claim corresponding to system claim 5 and is rejected on the same grounds as claim 5.
Claim 18 is the non-transitory computer-readable storage medium claim corresponding to system claim 5 and is rejected on the same grounds as claim 5.
Regarding claim 6, Yeh teaches the system of claim 1 where Yeh also teaches
determining that the first physical block (first physical block = Fig. 11 physical erasing unit 410(2)) comprises existing valid data (Yeh teaches there is valid data (in physical erasing unit 410(2)) that is copied to physical erasing unit 410(0) (see ¶[92]).)
Claim 13 is the method claim corresponding to system claim 6 and is rejected on the same grounds as claim 6.
Claim 19 is the non-transitory computer-readable storage medium claim corresponding to system claim 6 and is rejected on the same grounds as claim 6.
Regarding claim 7, Yeh teaches the system of claim 1 where Yeh also teaches
designating the first physical block (first physical block = Fig. 11 physical erasing unit 410(0)) and the second physical block (second physical block = physical erasing unit 410(5) for garbage collection (garbage collection = copying valid data to erasing block) (Yeh teaches merging operation that merges, into physical erasing unit 410(0), valid data from physical erasing unit 410(2) and physical erasing unit 410(6), wherein said physical erasing unit 410(2) is subsequently erased (see Fig. 18, ¶[92]). Note that in Fig. 18, UD3 in physical erasing unit 410(5) has been copied over to physical erasing unit 410(0).)
Claim 14 is the method claim corresponding to system claim 7 and is rejected on the same grounds as claim 7.
Claim 20 is the non-transitory computer-readable storage medium claim corresponding to system claim 7 and is rejected on the same grounds as claim 7.
Response to Remarks
Double patenting rejection is withdrawn in view of Applicant’s filing of terminal disclaimer on 22 June 2026.
Applicant’s remarks with respect to prior art rejection has been considered but are not persuasive. Applicant alleges that Yeh fails to teach write request’s ending logical address relative to ending address of partially aligned translation unit because Yeh’s first logical page is middle (and not ending address) of translation unit. Applicant’s remarks are not commensurate in scope with the claims. The claims do not recite said write request’s ending logical address is relative to said ending address of said partially aligned translation unit. Rather, the claim merely requires that said write request’s ending logical address not correspond (or isn’t) said ending address of said partially aligned translation unit. Therefore, Yeh’s teaching of said first logical page that is middle (which is also not ending address) of said translation unit, reads on the claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims (see In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993)). If Applicant intends for said write request’s ending logical address to be relative to said ending address of said partially aligned translation unit, the claims would need to be amended accordingly (provided adequate written support in the instant specification).
Additional Remarks
Karaje (US 20170293426) teaches determining that ending address of a write is unaligned due to said ending address not a multiple of B (see Karaje, Fig. 2, ¶[38]). This appears relevant to claims 1, 8 and 15.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHIE YEW/ Primary Examiner, Art Unit 2139
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