DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Priority
Regarding claims 1 – 20, “linking, in the translation map, the first entry and the second entry” is not entitled to priority of parent applications 16/943,387 and 17/887,300. As noted below, the limitation in question lacks written description in the instant specification. Since instant application is continuation of said parent applications, the same specification is found in said parent applications as well. As such, said parent applications also lack written description for the limitation in question. Therefore, the limitation in question is not entitled to priority of said parent applications.
Claim Interpretation
Regarding claims 1 – 20, “linking, in the translation map, the first entry and the second entry” refers to linking first and second entries that are in translation map (see spec Fig. 3, ¶[60]). There is no support for said linking itself being in said translation map, and thus interpreting said linking as being within said translation map, would be inconsistent with the instant specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 6 of U.S. Patent No. US 11,467,976 in view of Yeh. The claims at issue are obvious over Patent ‘976 in view of Yeh as outlined below.
Instant Application
Patent 11,467,976
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining that a write request references a partially aligned translation unit;
identifying a first entry in a translation map, wherein the first entry identifies a first physical block of the memory device, wherein the first physical block is mapped to the partially aligned translation unit;
creating a second entry in the translation map, wherein the second entry identifies a second physical block of the memory device, wherein the second physical block is mapped to the partially aligned translation unit;
linking, in the translation map, the first entry and the second entry; and
writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block.
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining that at least one portion of a write request, to a first translation unit of a plurality of translation units, does not align fully with the first translation unit;
identifying a first entry in a translation map, the translation map comprising a plurality of entries, each entry mapping a translation unit of the plurality of translation units to a corresponding physical block of a plurality of physical blocks, wherein the first entry identifies a first physical block corresponding to the first translation unit;
creating a second entry in the translation map, wherein the second entry identifies a second physical block of the plurality of physical blocks;
linking the second entry to the first entry, such that the first entry and second entry correspond to the first translation unit;
writing, to a portion of the second physical block associated with the portion of the first translation unit that aligns with the at least one portion of the write request, a set of data corresponding to the at least one portion of the write request;
2. The system of claim 1, wherein the partially aligned translation unit comprises a predefined number of logical pages and represents a base granularity of data supported by the memory device.
2. The system of claim 1, wherein the first translation unit comprises a predefined number of logical pages and represents a base granularity of data managed by the memory device.
3. The system of claim 1, wherein determining that the write request references a partially aligned translation unit further comprises:
determining that a starting logical address specified by the write request does not correspond to a starting address of the partially aligned translation unit.
3. The system of claim 1, determining that the at least one portion the write request does not align fully with the first translation unit further comprises:
determining that a starting logical address indicated in the write request does not correspond to a starting address of the first translation unit.
5. The system of claim 1, wherein the partially aligned translation unit is a last element of a set of translation units specified by the write request.
4. The system of claim 1, wherein the at least one portion of the write request is a last element of a set of translation units specified by the write request.
6. The system of claim 1, wherein the operations further comprise:
determining that the first physical block comprises existing valid data.
5. The system of claim 1, wherein the processing device is further to perform operations comprising:
determining that the first physical block comprises existing valid data.
7. The system of claim 1, wherein the operations further comprise:
designating the first physical block and the second physical block for garbage collection.
6. The system of claim 1, wherein the processing device is further to perform operations comprising:
designating the first physical block and the second physical block as priority for garbage collection.
Patent 11,467,976 recites system claims 1 – 6 that perform operations (or method) in said system claims. Therefore, said system claims 1 – 6 also map (in similar manner described supra) to corresponding method claims 8 – 10 and 12 – 14 of instant application.
Patent 11,467,976 recites base system claims 1 – 6 that perform operations in said base system claims that map (in similar manner described supra) to corresponding operations in claims 15 – 20. The claimed invention improves upon said base system by also having said operations also be performed by executing instructions in storage medium.
This improvement to said base system is merely an application of known technique from Yeh – memory controller 104 performing operations by executing control commands (see Yeh ¶[41]) in ROM (see Yeh ¶[48]).
One of ordinary skill in the art would recognize that this known technique of executing commands to implement operations can also be applied to said Patent ‘976’s operations, and the result would have been predictable. In this instance, said Patent ‘976’s operations would be performed by executing commands (instructions) in ROM (non-transitory computer-readable storage medium). It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Yeh’s known technique would have yielded i) predictable result of said Patent ‘976’s operations being performed by executing commands (instructions) in ROM (non-transitory computer-readable storage medium), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 4, Patent 11,467,976 teaches a base system with write request that references partially aligned translation unit (see claim 1). The claimed invention improves upon said base system where said write request’s ending logical address does not correspond to ending address of partially aligned translation unit.
This improvement to said base system is merely an application of known technique from Yeh – write to logical page (ending address) that is in middle of logical block (partially aligned translation unit) that has last logical page (ending address) (see Yeh Fig. 11, ¶[73]). Note that when there is only one logical page to write said logical page is also first and last.
One of ordinary skill in the art would recognize that this known technique of writing to a middle logical page of a logical block can also be applied to said write request to said partially aligned translation unit, and the result would have been predictable. In this instance, said write request to said partially aligned translation would write to a middle logical page of said partially aligned translation unit that has a last logical page. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Yeh’s known technique would have yielded i) predictable result of said write request to said partially aligned translation would write to a middle logical page (ending address) of said partially aligned translation unit that has a last logical page (ending address), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claim 11 is the method claim corresponding to system claim 4 and is rejected on the same grounds as claim 4.
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 20 of U.S. Patent No. US 12,346,263. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims at issue are anticipated by Patent ‘263 as outlined below.
Instant Application
Patent 12,346,263
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining that a write request references a partially aligned translation unit;
identifying a first entry in a translation map, wherein the first entry identifies a first physical block of the memory device, wherein the first physical block is mapped to the partially aligned translation unit;
creating a second entry in the translation map, wherein the second entry identifies a second physical block of the memory device, wherein the second physical block is mapped to the partially aligned translation unit;
linking, in the translation map, the first entry and the second entry; and
writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block.
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining that a write request references a partially aligned translation unit,
identifying a first entry in the translation map, wherein the first entry identifies a first physical block mapped to the partially aligned translation unit;
creating a second entry in the translation map, wherein the second entry identifies a second physical block mapped to the partially aligned translation unit, and wherein a pointer points from the first entry to the second entry;
writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block;
8. A method comprising:
determining, by a processing device, that a write request references a partially aligned translation unit;
identifying a first entry in a translation map, wherein the first entry identifies a first physical block of a memory device, wherein the first physical block is mapped to the partially aligned translation unit;
creating a second entry in the translation map, wherein the second entry identifies a second physical block of the memory device, wherein the second physical block is mapped to the partially aligned translation unit;
linking, in the translation map, the first entry and the second entry; and
writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block.
8. A method comprising:
determining, by a processing device, that a write request references a partially aligned translation unit,
identifying a first entry in the translation map, wherein the first entry identifies a first physical block mapped the partially aligned translation unit;
creating a second entry in the translation map, wherein the second entry identifies a second physical block mapped to the partially aligned translation unit, and
wherein a pointer points from the first entry to the second entry;
writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block
15. A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to:
determining that a write request references a partially aligned translation unit;
identifying a first entry in a translation map, wherein the first entry identifies a first physical block of the memory device, wherein the first physical block is mapped to the partially aligned translation unit;
creating a second entry in the translation map, wherein the second entry identifies a second physical block of the memory device, wherein the second physical block is mapped to the partially aligned translation unit;
linking, in the translation map, the first entry and the second entry; and
writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block.
15. A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to:
determine that a write request references a partially aligned translation unit,
identify a first entry in the translation map, wherein the first entry identifies a first physical block mapped to the partially aligned translation unit;
create a second entry in the translation map, wherein the second entry identifies a second physical block mapped to the partially aligned translation unit, and
wherein a pointer points from the first entry to the second entry;
write a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block; and
Claims 2 – 7 map to claims 2 – 7 of Patent ‘263.
Claims 9 – 14 map to claims 9 – 14 of Patent ‘263.
Claims 16 – 20 map to claims 16 – 20 of Patent ‘263.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, “linking, in the translation map, the first entry and the second entry” is not supported in the instant specification. An original claim may lack written description support when said original claim defines the invention in functional language specifying a desired result but the disclosure fails to sufficiently identify how the function is performed or the result is achieved (see MPEP 2163.03(V)). In this instance, the limitation in question refers to function of said linking (between said first and second entries) occurring within said translation map but the instant specification fails to disclose how said linking is to occur within said translation map. Rather, the instant specification discloses that said linking occurs outside of said translation map (see spec Fig. 2, ¶[60]). Therefore, the limitation in question, as originally filed, lacks written support.
Claim 8 is the method claim corresponding to system claim 1, and is rejected on the same grounds as claim 1.
Claim 15 is the non-transitory computer-readable storage medium claim corresponding to system claim 1, and is rejected on the same grounds as claim 1.
Claims, dependent upon independent claims 1, 8 or 15, are also rejected on the same grounds as said independent claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeh (US 20140372668).
Regarding claim 1, Yeh teaches
A system comprising:
a memory device; (memory device = Fig. 4 non-volatile memory module 106)
and a processing device (processing device = Fig. 4 memory controller 104), operatively coupled with the memory device, to perform operations comprising: (Yeh teaches memory controller 104 performing operations on nvm module 106 (see ¶[41]))
determining that a write request (write request = first logical page of LBA(2) to be updated with updated data UD3) references a partially aligned translation unit (partially aligned translation unit = LBA(2)); (Examiner is interpreting “partially aligned translation unit” to refer to translation unit that can be partially written to (see spec Fig. 3 TU 0 partially written).) (Yeh teaches determining that first logical page of LBA(2) (partially aligned translation unit) is to be updated with updated data UD3 (see Fig. 11, ¶[73]), wherein said LBA(2) is configured/predefined with 3 logical pages (see Fig. 11, ¶[63]). Note that only a portion (partially) (namely said first logical page) of said LBA(2) is written to.)
identifying a first entry in a translation map (translation map = logical-to-physical address mapping table + global random area searching table 800), wherein the first entry identifies a first physical block (first physical block = Fig. 11 physical erasing unit 410(2)) of the memory device, wherein the first physical block is mapped to the partially aligned translation unit; (Yeh teaches recording, in logical-to-physical address mapping table, relationship between logical units LBA(0)-LBA(4) and physical erasing units 410(0)-410(4) (see Fig. 8, ¶[70]) wherein said physical erasing units 410(0)-410(4) are in non-volatile memory 106 (memory device) (see Fig. 4, ¶[42]). Note that there is a first mapping (first entry) between LBA(2) (partially aligned translation unit) and physical erasing unit 410(2) (first physical block).)
creating a second entry in the translation map (translation map = logical-to-physical address mapping table + global random area searching table 800), wherein the second entry identifies a second physical block (second physical block = physical erasing unit 410(5)) of the memory device, wherein the second physical block is mapped to the partially aligned translation unit;
linking, in the translation map, the first entry and the second entry; (Yeh teaches building, in global random area search table 800, root unit 810(2) (second entry) (see ¶[77]) with an entry that maps (mapped) said first logical page of LBA(2) (partially aligned translation unit) (or LBA(2)-1) to second physical programming unit of physical erasing unit 410(5) (second physical block) (or 410(5)-2) (see Fig. 15, ¶[84]) wherein said physical erasing unit 410(5) is in non-volatile memory (memory device) 106 (see Fig. 4, ¶[42]). Note that LBA(2)-1 includes LBA(2) which is also in said first mapping (first entry) between LBA(2) and physical erasing unit 410(2). In other words, LBA(2) links (linking) said root unit 810(2) (second entry) with said first mapping (first entry).)
writing a subset of data corresponding to the partially aligned translation unit to a first portion to the second physical block (Yeh teaches if first logical page of LBA(2) (partially aligned translation units) is to be updated with updated data UD3 (subset of data), issuing programming command to write said UD3 to said second physical programming unit (first portion) of said physical erasing unit 410(5) (second physical block) (see Fig. 11, ¶[73]).)
Claim 8 is the method claim corresponding to system claim 1 and is rejected on the same grounds as claim 1.
Claim 15 is the non-transitory computer-readable storage medium claim corresponding to system claim 1 and is rejected on the same grounds as claim 1. Yeh also teaches
A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device processing device = Fig. 4 memory controller 104), cause the processing device to: (Yeh teaches memory controller 104 includes memory management circuit (see ¶[46]) that includes a microprocessor that executes control instructions in ROM (see ¶[48]).)
Regarding claim 2, Yeh teaches the system of claim 1 where Yeh also teaches
wherein the partially aligned translation unit comprises a predefined number of logical pages and represents a base granularity of data managed by the memory device (Yeh teaches LBA(2) (partially aligned translation unit) configured/predefined with logical pages (see ¶[63]) where Fig. 11 discloses an embodiment of 3 logical pages (predefined number of logical pages) for LBA(2). Yeh also teaches that said logical pages are mapped to physical programming units of physical erasing unit (see Fig. 8, ¶[70]) (in nvm module 106 (memory device) (see Fig. 4)) wherein physical programming unit is minimum unit (base granularity) for writing data (see ¶[43]).)
Claim 9 is the method claim corresponding to system claim 2 and is rejected on the same grounds as claim 2.
Claim 16 is the non-transitory computer-readable storage medium claim corresponding to system claim 2 and is rejected on the same grounds as claim 2.
Regarding claim 3, Yeh teaches the system of claim 1 where Yeh also teaches
wherein determining that the write request references the partially aligned translation unit further comprises:
determining that a starting logical address specified by the write request (write request = first logical page of LBA(2) to be updated with updated data UD3) does not correspond to a starting address of the partially aligned translation unit (Yeh teaches determining that first logical page (starting address) of LBA(2) is to be updated with updated data UD3 (see Fig. 11, ¶[73]). Note that in Fig. 11, said first logical page is in middle of LBA(2) (partially aligned translation unit) and not at zeroth logical page (starting address) of LBA(2).)
Claim 10 is the method claim corresponding to system claim 3 and is rejected on the same grounds as claim 3.
Claim 17 is the non-transitory computer-readable storage medium claim corresponding to system claim 3 and is rejected on the same grounds as claim 3.
Regarding claim 4, Yeh teaches the system of claim 1 where Yeh also teaches
wherein determining that the write request references the partially aligned translation unit further comprises:
determining that an ending logical address specified by the write request (write request = first logical page of LBA(2) to be updated with updated data UD3) does not correspond to an ending address of the partially aligned translation unit (Yeh teaches determining that first logical page of LBA(2) is to be updated with updated data UD3 (see Fig. 11, ¶[73]). Note that in Fig. 11, said first logical page is in middle of LBA(2) (partially aligned translation unit) and not at second logical page (ending address) of LBA(2). Further note that said first logical page of LBA(2) is also one and only (i.e. first and last) update to LBA(2). Therefore, said first logical page of LBA(2) is also ending address (ending logical address).)
Claim 11 is the method claim corresponding to system claim 4 and is rejected on the same grounds as claim 4.
Regarding claim 5, Yeh teaches the system of claim 1 where Yeh also teaches
wherein the partially aligned translation unit is a last element of a set of translation units specified by the write request (write request = first logical page of LBA(2) to be updated with updated data UD3) (Examiner is interpreting “set of translation units” to be set of “1”.) (Yeh teaches determining that first logical page of LBA(2) (partially aligned translation unit) is to be updated with updated data UD3 (see Fig. 11, ¶[73]). Note that in Fig. 11, LBA(2) is one and only (i.e. first and last) block (set of translation units) to be updated. Therefore, LBA(2) is also last block (last element) to be updated.)
Claim 12 is the method claim corresponding to system claim 5 and is rejected on the same grounds as claim 5.
Claim 18 is the non-transitory computer-readable storage medium claim corresponding to system claim 5 and is rejected on the same grounds as claim 5.
Regarding claim 6, Yeh teaches the system of claim 1 where Yeh also teaches
determining that the first physical block (first physical block = Fig. 11 physical erasing unit 410(2)) comprises existing valid data (Yeh teaches there is valid data (in physical erasing unit 410(2)) that is copied to physical erasing unit 410(0) (see ¶[92]).)
Claim 13 is the method claim corresponding to system claim 6 and is rejected on the same grounds as claim 6.
Claim 19 is the non-transitory computer-readable storage medium claim corresponding to system claim 6 and is rejected on the same grounds as claim 6.
Regarding claim 7, Yeh teaches the system of claim 1 where Yeh also teaches
designating the first physical block (first physical block = Fig. 11 physical erasing unit 410(0)) and the second physical block (second physical block = physical erasing unit 410(5) for garbage collection (garbage collection = copying valid data to erasing block) (Yeh teaches merging operation that merges, into physical erasing unit 410(0), valid data from physical erasing unit 410(2) and physical erasing unit 410(6), wherein said physical erasing unit 410(2) is subsequently erased (see Fig. 18, ¶[92]). Note that in Fig. 18, UD3 in physical erasing unit 410(5) has been copied over to physical erasing unit 410(0).)
Claim 14 is the method claim corresponding to system claim 7 and is rejected on the same grounds as claim 7.
Claim 20 is the non-transitory computer-readable storage medium claim corresponding to system claim 7 and is rejected on the same grounds as claim 7.
Additional Remarks
In the interest of compact prosecution, in order to address §112(a) written description, claims 1, 8 and 15 should be amended to “linking
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139