DETAILED ACTION
This Action is responsive to the Application filed on 01/08/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 7-9, 14-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mozak et al. (US 20140095947 A1)(hereafter referred to as Mozak) further in view of Kanteti (US 20220244869 A1)(hereafter referred to as Kanteti).
Regarding Claim 1,
Mozak discloses the following limitations:
A system (Fig. 1) comprising:
memory(¶0121); and a processing device (¶0122), operatively coupled with the memory, to perform operations comprising (¶¶0121-122):
generating (Fig. 6, steps 606 - 616) a simulated workload for a memory sub-system (Memory Device 110, Fig. 1), the simulated workload comprising a series of input/output (I/O) commands (“memory access transactions” [0089]) directed to respective logical block addresses (“an address range” [0089] // ¶0046) associated with the memory sub-system (“The test source generates a test software command … The test engine selects an address range … being provided the address range by the test source. The test engine iterates through the test for each of the addresses. For each iteration, the test engine generates one or more memory access transactions to pass to the memory controller” [0087-89] // ¶¶0045-46; 0086) – As taught in Fig. 6, a test engine generates memory access transactions associated with an address range (i.e., “logical block addresses”; see ¶¶0045-46) received from a test source. As clarified in ¶0086, the address range received from the test source enables a memory test to be performed on the memory device (i.e., “a simulated workload”).--;
associating the respective logical block addresses (“The memory access transactions can include memory command identifiers to carry out the test software command, as well as a specific address location” [0089]) – As taught in ¶0089, for each address in received address range, the test engine generates associated memory access transactions including both “memory command identifiers” and specific memory address locations.-- …; and
issuing (Fig. 6, step 618) the series of input/output commands to the memory sub-system to cause the memory sub-system to perform corresponding memory access operations on data (“The test engine passes the transaction or sequence of transactions to the memory controller to cause the memory controller to schedule the transactions … the memory device executes the memory device commands to carry out the transaction(s)” [0090])
Mozak is silent regarding memory device 110 storing files associated with a file system. Specifically, Mozak is silent regarding the following limitations:
associating the respective logical block addresses with files in a file system
memory access operations on data representing the files in the file system
However, Kanteti discloses the following limitations:
associating the respective logical block addresses with files in a file system (“the kernel of the host can directly cause the file system data to be written to physical addresses of individual zones and thus map logical addresses to physical addresses of sequentially-written zones” [0018] // ¶¶0033; 0039-40; 0044 // Fig. 1) – As shown in Kanteti Fig. 1, a memory sub-system 110 receives commands from a host 120 to perform operations on memory device 130, similar to how the system 100 of Mozak Fig. 1 receives commands from a test source 160 to perform operations on a memory device 110. Examiner accordingly considers the storage systems depicted in Kanteti and Mozak Figs. 1 as analogous. As taught in Kanteti, each logical address in a memory system is associated with a file system object--,
memory access operations on data (“file system data” [0040]) representing the files in the file system (¶¶0039-40) – As taught in Kanteti, memory access operations such as reads and writes are performed on file system data.
Mozak and Kanteti are considered analogous to the claimed invention because they all relate to the same field of logical address mapping management in storage environments receiving memory access commands from external sources. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mozak with the teachings of Kanteti and realize memory system whereby a processor associates logical block addresses with files of a file system. Mapping logical addresses to files of a file system improves performance by enabling a host device to perform address translation for memory access operations prior to sending the memory access operation to the memory device, reducing a processing load of the memory device, as disclosed in Kanteti ¶0018: “Further, in some embodiments, the kernel of the host operating system includes device mapping logic that can directly cause the file system data to be written to physical addresses of individual zones and thus map logical addresses to physical addresses of sequentially-written zones, by-passing the need for the memory sub-system controller to handle this mapping.” [0018]
Regarding Claim 2,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 2. The combined teachings of Mozak and Kanteti disclose the following limitations:
The system of claim 1 (see Claim 1 limitation mappings above), wherein the series of input/output commands comprises at least one program command (Mozak, ¶0020; Kanteti, ¶0060) to program data associated with a file to the memory sub-system (Mozak, “The test engine as described can inject transactions (e.g., read, write, maintenance command) directly into the memory controller” [0020]) – As taught in Mozak ¶0020, memory transactions which are sent to the memory controller include write transactions (i.e., “at least one program command”). See also Kanteti ¶0060.-- and
at least one erase command (Kanteti, ¶0060) to erase at least a portion of the data associated with the file from the memory sub-system. (Kanteti, “Each of the write requests 342 can correspond to one or more commands … and the commands can be for a write … erase … or a combination thereof” [0060]) – As clarified in Kanteti ¶0060, several transactions including a write and an erase can be performed in combination on a memory device.
Regarding Claim 7,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 7. The combined teachings of Mozak and Kanteti disclose the following limitations:
The system of claim 1, wherein the file system comprises an open source, log-structured file system (Kanteti, “applications … can include a log structure merge (LSM)- based architecture” [0058] // ¶¶0018; 0061) – As taught in Kanteti, varieties of file system formats, including an “LSM-based” architecture (¶0058); formats where data are stored in “logs” (¶0061); and formats where data are written sequentially (¶0018) can be employed by the storage system. Examiner considers such an architecture of file system data organization as reading on the claimed concept of “an open source, log-structured file system” under the BRI of the claimed language.
Regarding Claim 8,
Mozak discloses the following limitations:
A method comprising:
generating (Fig. 6, steps 606 - 616) a simulated workload for a memory sub-system (Memory Device 110, Fig. 1), the simulated workload comprising a series of input/output (I/O) commands (“memory access transactions” [0089]) directed to respective logical block addresses (“an address range” [0089] // ¶0046) associated with the memory sub-system (“The test source generates a test software command … The test engine selects an address range … being provided the address range by the test source. The test engine iterates through the test for each of the addresses. For each iteration, the test engine generates one or more memory access transactions to pass to the memory controller” [0087-89] // ¶¶0045-46; 0086) – As taught in Fig. 6, a test engine generates memory access transactions associated with an address range (i.e., “logical block addresses”; see ¶¶0045-46) received from a test source. As clarified in ¶0086, the address range received from the test source enables a memory test to be performed on the memory device (i.e., “a simulated workload”).--;
associating the respective logical block addresses (“The memory access transactions can include memory command identifiers to carry out the test software command, as well as a specific address location” [0089]) – As taught in ¶0089, for each address in received address range, the test engine generates associated memory access transactions including both “memory command identifiers” and specific memory address locations.-- …; and
issuing (Fig. 6, step 618) the series of input/output commands to the memory sub-system to cause the memory sub-system to perform corresponding memory access operations on data (“The test engine passes the transaction or sequence of transactions to the memory controller to cause the memory controller to schedule the transactions … the memory device executes the memory device commands to carry out the transaction(s)” [0090])
Mozak is silent regarding memory device 110 storing files associated with a file system. Specifically, Mozak is silent regarding the following limitations:
associating the respective logical block addresses with files in a file system
memory access operations on data representing the files in the file system
However, Kanteti discloses the following limitations:
associating the respective logical block addresses with files in a file system (“the kernel of the host can directly cause the file system data to be written to physical addresses of individual zones and thus map logical addresses to physical addresses of sequentially-written zones” [0018] // ¶¶0033; 0039-40; 0044 // Fig. 1) – As shown in Kanteti Fig. 1, a memory sub-system 110 receives commands from a host 120 to perform operations on memory device 130, similar to how the system 100 of Mozak Fig. 1 receives commands from a test source 160 to perform operations on a memory device 110. Examiner accordingly considers the storage systems depicted in Kanteti and Mozak Figs. 1 as analogous. As taught in Kanteti, each logical address in a memory system is associated with a file system object--,
memory access operations on data (“file system data” [0040]) representing the files in the file system (¶¶0039-40) – As taught in Kanteti, memory access operations such as reads and writes are performed on file system data.
Mozak and Kanteti are considered analogous to the claimed invention because they all relate to the same field of logical address mapping management in storage environments receiving memory access commands from external sources. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mozak with the teachings of Kanteti and realize memory system whereby a processor associates logical block addresses with files of a file system. Mapping logical addresses to files of a file system improves performance by enabling a host device to perform address translation for memory access operations prior to sending the memory access operation to the memory device, reducing a processing load of the memory device, as disclosed in Kanteti ¶0018: “Further, in some embodiments, the kernel of the host operating system includes device mapping logic that can directly cause the file system data to be written to physical addresses of individual zones and thus map logical addresses to physical addresses of sequentially-written zones, by-passing the need for the memory sub-system controller to handle this mapping.” [0018]
Regarding Claim 9,
The same motivation to combine provided in Claim 8 is equally applicable to Claim 9. The combined teachings of Mozak and Kanteti disclose the following limitations:
The method of claim 8 (see Claim 8 limitation mappings above), wherein the series of input/output commands comprises at least one program command (Mozak, ¶0020; Kanteti, ¶0060) to program data associated with a file to the memory sub-system (Mozak, “The test engine as described can inject transactions (e.g., read, write, maintenance command) directly into the memory controller” [0020]) – As taught in Mozak ¶0020, memory transactions which are sent to the memory controller include write transactions (i.e., “at least one program command”). See also Kanteti ¶0060.-- and
at least one erase command (Kanteti, ¶0060) to erase at least a portion of the data associated with the file from the memory sub-system. (Kanteti, “Each of the write requests 342 can correspond to one or more commands … and the commands can be for a write … erase … or a combination thereof” [0060]) – As clarified in Kanteti ¶0060, several transactions including a write and an erase can be performed in combination on a memory device.
Regarding Claim 14,
The same motivation to combine provided in Claim 8 is equally applicable to Claim 14. The combined teachings of Mozak and Kanteti disclose the following limitations:
The method of claim 8, wherein the file system comprises an open source, log-structured file system (Kanteti, “applications … can include a log structure merge (LSM)- based architecture” [0058] // ¶¶0018; 0061) – As taught in Kanteti, varieties of file system formats, including an “LSM-based” architecture (¶0058); formats where data are stored in “logs” (¶0061); and formats where data are written sequentially (¶0018) can be employed by the storage system. Examiner considers such an architecture of file system data organization as reading on the claimed concept of “an open source, log-structured file system” under the BRI of the claimed language.
Regarding Claim 15,
Mozak discloses the following limitations:
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising (¶0092):
generating (Fig. 6, steps 606 - 616) a simulated workload for a memory sub-system (Memory Device 110, Fig. 1), the simulated workload comprising a series of input/output (I/O) commands (“memory access transactions” [0089]) directed to respective logical block addresses (“an address range” [0089] // ¶0046) associated with the memory sub-system (“The test source generates a test software command … The test engine selects an address range … being provided the address range by the test source. The test engine iterates through the test for each of the addresses. For each iteration, the test engine generates one or more memory access transactions to pass to the memory controller” [0087-89] // ¶¶0045-46; 0086) – As taught in Fig. 6, a test engine generates memory access transactions associated with an address range (i.e., “logical block addresses”; see ¶¶0045-46) received from a test source. As clarified in ¶0086, the address range received from the test source enables a memory test to be performed on the memory device (i.e., “a simulated workload”).--;
associating the respective logical block addresses (“The memory access transactions can include memory command identifiers to carry out the test software command, as well as a specific address location” [0089]) – As taught in ¶0089, for each address in received address range, the test engine generates associated memory access transactions including both “memory command identifiers” and specific memory address locations.-- …; and
issuing (Fig. 6, step 618) the series of input/output commands to the memory sub-system to cause the memory sub-system to perform corresponding memory access operations on data (“The test engine passes the transaction or sequence of transactions to the memory controller to cause the memory controller to schedule the transactions … the memory device executes the memory device commands to carry out the transaction(s)” [0090])
Mozak is silent regarding memory device 110 storing files associated with a file system. Specifically, Mozak is silent regarding the following limitations:
associating the respective logical block addresses with files in a file system
memory access operations on data representing the files in the file system
However, Kanteti discloses the following limitations:
associating the respective logical block addresses with files in a file system (“the kernel of the host can directly cause the file system data to be written to physical addresses of individual zones and thus map logical addresses to physical addresses of sequentially-written zones” [0018] // ¶¶0033; 0039-40; 0044 // Fig. 1) – As shown in Kanteti Fig. 1, a memory sub-system 110 receives commands from a host 120 to perform operations on memory device 130, similar to how the system 100 of Mozak Fig. 1 receives commands from a test source 160 to perform operations on a memory device 110. Examiner accordingly considers the storage systems depicted in Kanteti and Mozak Figs. 1 as analogous. As taught in Kanteti, each logical address in a memory system is associated with a file system object--,
memory access operations on data (“file system data” [0040]) representing the files in the file system (¶¶0039-40) – As taught in Kanteti, memory access operations such as reads and writes are performed on file system data.
Mozak and Kanteti are considered analogous to the claimed invention because they all relate to the same field of logical address mapping management in storage environments receiving memory access commands from external sources. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mozak with the teachings of Kanteti and realize memory system whereby a processor associates logical block addresses with files of a file system. Mapping logical addresses to files of a file system improves performance by enabling a host device to perform address translation for memory access operations prior to sending the memory access operation to the memory device, reducing a processing load of the memory device, as disclosed in Kanteti ¶0018: “Further, in some embodiments, the kernel of the host operating system includes device mapping logic that can directly cause the file system data to be written to physical addresses of individual zones and thus map logical addresses to physical addresses of sequentially-written zones, by-passing the need for the memory sub-system controller to handle this mapping.” [0018]
Regarding Claim 16,
The same motivation to combine provided in Claim 15 is equally applicable to Claim 16. The combined teachings of Mozak and Kanteti disclose the following limitations:
The non-transitory computer-readable storage medium of claim 15 (see Claim 15 limitation mappings above), wherein the series of input/output commands comprises at least one program command (Mozak, ¶0020; Kanteti, ¶0060) to program data associated with a file to the memory sub-system (Mozak, “The test engine as described can inject transactions (e.g., read, write, maintenance command) directly into the memory controller” [0020]) – As taught in Mozak ¶0020, memory transactions which are sent to the memory controller include write transactions (i.e., “at least one program command”). See also Kanteti ¶0060.-- and
at least one erase command (Kanteti, ¶0060) to erase at least a portion of the data associated with the file from the memory sub-system. (Kanteti, “Each of the write requests 342 can correspond to one or more commands … and the commands can be for a write … erase … or a combination thereof” [0060]) – As clarified in Kanteti ¶0060, several transactions including a write and an erase can be performed in combination on a memory device.
Regarding Claim 20,
The same motivation to combine provided in Claim 15 is equally applicable to Claim 20. The combined teachings of Mozak and Kanteti disclose the following limitations:
The non-transitory computer-readable storage medium of claim 15, wherein the file system comprises an open source, log-structured file system (Kanteti, “applications … can include a log structure merge (LSM)- based architecture” [0058] // ¶¶0018; 0061) – As taught in Kanteti, varieties of file system formats, including an “LSM-based” architecture (¶0058); formats where data are stored in “logs” (¶0061); and formats where data are written sequentially (¶0018) can be employed by the storage system. Examiner considers such an architecture of file system data organization as reading on the claimed concept of “an open source, log-structured file system” under the BRI of the claimed language.
Claims 3-4, 10-11, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Mozak further in view of Kanteti and Jin et al. (US 20220229772 A1)(hereafter referred to as Jin).
Regarding Claim 3,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 3. The combined teachings of Mozak and Kanteti disclose the following limitations:
The system of claim 2 (see Claim 2 limitation mappings above),
Although Mozak ¶0046 and Kanteti ¶0047 generally disclose instances of logical-to-physical address mapping management, the combined teaching of Mozak and Kanteti do not explicitly disclose the following limitations:
wherein responsive to receiving the program command, the memory sub-system is to generate a plurality of entries in an address mapping table to map the respective logical block addresses associated with the file to physical addresses where the data is stored on the memory sub-system.
However, Jin discloses the following limitations:
wherein responsive to receiving the program command, the memory sub-system is to generate a plurality of entries in an address mapping table (“L2P map table” + “P2L map table” [0065]) to map the respective logical block addresses associated with the file to physical addresses where the data is stored on the memory sub-system. (“after the controller 130 programs new user data to the memory device 150, the controller 130 may generate a P2L map entry for linking a physical address, which indicates the location where the new user data is programmed in the memory device 150, to a logical address input from the host 102 … After that, the controller 130 may update the L2P map table stored in the memory device 150 based on the P2L map entry.” [0066-68] // ¶0065) – As taught in Jin, a memory controller 130 updates entries in both a P2L map table and an L2P map table in response to a program operation to write new user data into memory.
Mozak, Kanteti, and Jin are considered analogous to the claimed invention because they all relate to the same field of address mapping table management responsive to external host memory transactions. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mozak and Kanteti with the teachings of Jin and realize a system whereby address mapping table entries are generated in response to program operations performed on a memory. Doing so enables efficient control map data in environments where large numbers of L2P entries accrue over time, as disclosed in Jin ¶0070: “When the memory system 100 performs a data input/output operation, a new map entry may be generated and stored in the memory device 150 … As L2P map entries are sequentially added to the L2P map table, the size of the L2P map table can increase, and a plurality of L2P map entries may be mixed up. In order for the memory system 110 to efficiently control the map data, the map data controller 196 may re-configure the L2P map table stored in the memory device 150 after data input/output operations, the garbage collection or the like.” [0070]
Regarding Claim 4,
The same motivation to combine provided in Claim 3 is equally applicable to Claim 4. The combined teachings of Mozak, Kanteti, and Jin disclose the following limitations:
The system of claim 3, wherein responsive to receiving the erase command, the memory sub-system is to delete at least a subset of the plurality of entries in the address mapping table. (Jin, “When the host transmits an erase command to erase a data item … a map entry (e.g., a first map entry), which is met data associated with the data item, can be erased … the memory system 110 deletes the map entry” [0072]) – As taught in Jin, map entries are deleted in response to host erase commands.
Regarding Claim 10,
The same motivation to combine provided in Claim 8 is equally applicable to Claim 10. The combined teachings of Mozak and Kanteti disclose the following limitations:
The method of claim 9 (see Claim 9 limitation mappings above),
Although Mozak ¶0046 and Kanteti ¶0047 generally disclose instances of logical-to-physical address mapping management, the combined teaching of Mozak and Kanteti do not explicitly disclose the following limitations:
wherein responsive to receiving the program command, the memory sub-system is to generate a plurality of entries in an address mapping table to map the respective logical block addresses associated with the file to physical addresses where the data is stored on the memory sub-system.
However, Jin discloses the following limitations:
wherein responsive to receiving the program command, the memory sub-system is to generate a plurality of entries in an address mapping table (“L2P map table” + “P2L map table” [0065]) to map the respective logical block addresses associated with the file to physical addresses where the data is stored on the memory sub-system. (“after the controller 130 programs new user data to the memory device 150, the controller 130 may generate a P2L map entry for linking a physical address, which indicates the location where the new user data is programmed in the memory device 150, to a logical address input from the host 102 … After that, the controller 130 may update the L2P map table stored in the memory device 150 based on the P2L map entry.” [0066-68] // ¶0065) – As taught in Jin, a memory controller 130 updates entries in both a P2L map table and an L2P map table in response to a program operation to write new user data into memory.
Mozak, Kanteti, and Jin are considered analogous to the claimed invention because they all relate to the same field of address mapping table management responsive to external host memory transactions. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mozak and Kanteti with the teachings of Jin and realize a system whereby address mapping table entries are generated in response to program operations performed on a memory. Doing so enables efficient control map data in environments where large numbers of L2P entries accrue over time, as disclosed in Jin ¶0070: “When the memory system 100 performs a data input/output operation, a new map entry may be generated and stored in the memory device 150 … As L2P map entries are sequentially added to the L2P map table, the size of the L2P map table can increase, and a plurality of L2P map entries may be mixed up. In order for the memory system 110 to efficiently control the map data, the map data controller 196 may re-configure the L2P map table stored in the memory device 150 after data input/output operations, the garbage collection or the like.” [0070]
Regarding Claim 11,
The same motivation to combine provided in Claim 10 is equally applicable to Claim 11. The combined teachings of Mozak, Kanteti, and Jin disclose the following limitations:
The method of claim 10, wherein responsive to receiving the erase command, the memory sub-system is to delete at least a subset of the plurality of entries in the address mapping table. (Jin, “When the host transmits an erase command to erase a data item … a map entry (e.g., a first map entry), which is met data associated with the data item, can be erased … the memory system 110 deletes the map entry” [0072]) – As taught in Jin, map entries are deleted in response to host erase commands.
Regarding Claim 17,
The same motivation to combine provided in Claim 15 is equally applicable to Claim 17. The combined teachings of Mozak and Kanteti disclose the following limitations:
The non-transitory computer-readable storage medium of claim 16 (see Claim 16 limitation mappings above),
Although Mozak ¶0046 and Kanteti ¶0047 generally disclose instances of logical-to-physical address mapping management, the combined teaching of Mozak and Kanteti do not explicitly disclose the following limitations:
wherein responsive to receiving the program command, the memory sub-system is to generate a plurality of entries in an address mapping table to map the respective logical block addresses associated with the file to physical addresses where the data is stored on the memory sub-system.
However, Jin discloses the following limitations:
wherein responsive to receiving the program command, the memory sub-system is to generate a plurality of entries in an address mapping table (“L2P map table” + “P2L map table” [0065]) to map the respective logical block addresses associated with the file to physical addresses where the data is stored on the memory sub-system. (“after the controller 130 programs new user data to the memory device 150, the controller 130 may generate a P2L map entry for linking a physical address, which indicates the location where the new user data is programmed in the memory device 150, to a logical address input from the host 102 … After that, the controller 130 may update the L2P map table stored in the memory device 150 based on the P2L map entry.” [0066-68] // ¶0065) – As taught in Jin, a memory controller 130 updates entries in both a P2L map table and an L2P map table in response to a program operation to write new user data into memory.
Mozak, Kanteti, and Jin are considered analogous to the claimed invention because they all relate to the same field of address mapping table management responsive to external host memory transactions. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mozak and Kanteti with the teachings of Jin and realize a system whereby address mapping table entries are generated in response to program operations performed on a memory. Doing so enables efficient control map data in environments where large numbers of L2P entries accrue over time, as disclosed in Jin ¶0070: “When the memory system 100 performs a data input/output operation, a new map entry may be generated and stored in the memory device 150 … As L2P map entries are sequentially added to the L2P map table, the size of the L2P map table can increase, and a plurality of L2P map entries may be mixed up. In order for the memory system 110 to efficiently control the map data, the map data controller 196 may re-configure the L2P map table stored in the memory device 150 after data input/output operations, the garbage collection or the like.” [0070]
Regarding Claim 18,
The same motivation to combine provided in Claim 17 is equally applicable to Claim 18. The combined teachings of Mozak, Kanteti, and Jin disclose the following limitations:
The non-transitory computer-readable storage medium of claim 17, wherein responsive to receiving the erase command, the memory sub-system is to delete at least a subset of the plurality of entries in the address mapping table. (Jin, “When the host transmits an erase command to erase a data item … a map entry (e.g., a first map entry), which is met data associated with the data item, can be erased … the memory system 110 deletes the map entry” [0072]) – As taught in Jin, map entries are deleted in response to host erase commands.
Claims 5-6, 12-13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mozak further in view of Kanteti and Bhimani et al. (US 20190087300 A1)(hereafter referred to as Bhimani).
Regarding Claim 5,
The same motivation to combine provided in Claim 1 is equally applicable to Claim 5. The combined teachings of Mozak and Kanteti disclose the following limitations:
The system of claim 1 (see Claim 1 limitation mappings above),
The combined teachings of Mozak and Kanteti are silent regarding the following limitations:
wherein the processing device is to perform operations further comprising: receiving data representing write statistics of the memory sub-system in response to performance of the corresponding memory access operations.
However, Bhimani discloses the following limitations:
wherein the processing device is to perform operations further comprising: receiving (Fig. 6, step S650) data representing write statistics (“measurements” [0053]) of the memory sub-system in response to performance of the corresponding memory access operations (“When a representative workload is free of conflicts, the representative I/O generator … issues the I/Os to the SSDs (S640). The storage system and SSD performance may then be benchmarked (S650). The measurements may be displayed live as the representative I/O is being executed and may also be logged for later review. The measurements may include … endurance attributes (e.g., write amplification factor etc.).” [0053] // ¶0048 // Fig. 6) – As shown in Bhimani Fig. 6, a “representative workload” comprising a plurality of I/O commands are passed to an SSD in order to benchmark performance of the SSD (see ¶0048), similar to how the Memory Device 110 of Mozak Fig. 1 is tested using a plurality of memory access transactions. Examiner accordingly considers the SSD of Bhimani as analogous to memory device 110 of Mozak Fig. 1. As taught in Bhimani Fig. 6, after the plurality of I/O commands are issued to the SSD, corresponding “measurements” including “write amplification factor” (i.e., “write statistics”) are displayed and are logged for review.
Mozak, Kanteti, and Bhimani are all considered analogous to the claimed invention because they all relate to the same field of testing memory devices using plural memory access commands received from an external host. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mozak and Kanteti with the teachings of Bhimani and realize a system whereby write statics are received after performance of a series of corresponding memory access operations. Doing enables improved memory device benchmarking to be performed using real-world I/O patterns with a traditional benchmarking tool, as disclosed in Bhimani ¶0054: “Accordingly, the above described embodiments of the present disclosure provide for systems and methods for testing storage devices using a representative I/O generator. Unlike previous systems for performing storage device benchmarking, the system is able to simulate real-world application I/O instead of the overly simplistic I/O of current benchmarking tools. Representative I/O allows for performing benchmarking that has the ease-of-use of using a traditional benchmarking tool while still providing the performance of an actual application workload. Additionally, the storage requirements are minimal when compared to using application traces.” [0054]
Regarding Claim 6,
The same motivation to combine provided in Claim 5 is equally applicable to Claim 6. The combined teachings of Mozak, Kanteti, and Bhimani disclose the following limitations:
The system of claim 5 (see Claim 5 limitation mappings above), wherein the processing device is to perform operations further comprising: analyzing the data representing the write statistics to evaluate an endurance of the memory sub-system. (Bhimani, “The measurements may be displayed live … The measurements may include … endurance attributes (e.g. write amplification factor etc.)” [0053]) – As taught in Bhimani, write amplification factor enables the endurance of the SSD to be benchmarked.
Regarding Claim 12,
The same motivation to combine provided in Claim 8 is equally applicable to Claim 12. The combined teachings of Mozak and Kanteti disclose the following limitations:
The method of claim 8 (see Claim 8 limitation mappings above),
The combined teachings of Mozak and Kanteti are silent regarding the following limitations:
further comprising: receiving data representing write statistics of the memory sub-system in response to performance of the corresponding memory access operations.
However, Bhimani discloses the following limitations:
further comprising: receiving (Fig. 6, step S650) data representing write statistics (“measurements” [0053]) of the memory sub-system in response to performance of the corresponding memory access operations (“When a representative workload is free of conflicts, the representative I/O generator … issues the I/Os to the SSDs (S640). The storage system and SSD performance may then be benchmarked (S650). The measurements may be displayed live as the representative I/O is being executed and may also be logged for later review. The measurements may include … endurance attributes (e.g., write amplification factor etc.).” [0053] // ¶0048 // Fig. 6) – As shown in Bhimani Fig. 6, a “representative workload” comprising a plurality of I/O commands are passed to an SSD in order to benchmark performance of the SSD (see ¶0048), similar to how the Memory Device 110 of Mozak Fig. 1 is tested using a plurality of memory access transactions. Examiner accordingly considers the SSD of Bhimani as analogous to memory device 110 of Mozak Fig. 1. As taught in Bhimani Fig. 6, after the plurality of I/O commands are issued to the SSD, corresponding “measurements” including “write amplification factor” (i.e., “write statistics”) are displayed and are logged for review.
Mozak, Kanteti, and Bhimani are all considered analogous to the claimed invention because they all relate to the same field of testing memory devices using plural memory access commands received from an external host. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mozak and Kanteti with the teachings of Bhimani and realize a system whereby write statics are received after performance of a series of corresponding memory access operations. Doing enables improved memory device benchmarking to be performed using real-world I/O patterns with a traditional benchmarking tool, as disclosed in Bhimani ¶0054: “Accordingly, the above described embodiments of the present disclosure provide for systems and methods for testing storage devices using a representative I/O generator. Unlike previous systems for performing storage device benchmarking, the system is able to simulate real-world application I/O instead of the overly simplistic I/O of current benchmarking tools. Representative I/O allows for performing benchmarking that has the ease-of-use of using a traditional benchmarking tool while still providing the performance of an actual application workload. Additionally, the storage requirements are minimal when compared to using application traces.” [0054]
Regarding Claim 13,
The same motivation to combine provided in Claim 12 is equally applicable to Claim 13. The combined teachings of Mozak, Kanteti, and Bhimani disclose the following limitations:
The method of claim 12 (see Claim 12 limitation mappings above), further comprising: analyzing the data representing the write statistics to evaluate an endurance of the memory sub-system. (Bhimani, “The measurements may be displayed live … The measurements may include … endurance attributes (e.g. write amplification factor etc.)” [0053]) – As taught in Bhimani, write amplification factor enables the endurance of the SSD to be benchmarked.
Regarding Claim 19,
The same motivation to combine provided in Claim 15 is equally applicable to Claim 19. The combined teachings of Mozak and Kanteti disclose the following limitations:
The non-transitory computer-readable storage medium of claim 15 (see Claim 15 limitation mappings above),
The combined teachings of Mozak and Kanteti are silent regarding the following limitations:
further comprising: receiving data representing write statistics of the memory sub-system in response to performance of the corresponding memory access operations .
analyzing the data representing the write statistics to evaluate an endurance of the memory sub-system
However, Bhimani discloses the following limitations:
further comprising: receiving (Fig. 6, step S650) data representing write statistics (“measurements” [0053]) of the memory sub-system in response to performance of the corresponding memory access operations (“When a representative workload is free of conflicts, the representative I/O generator … issues the I/Os to the SSDs (S640). The storage system and SSD performance may then be benchmarked (S650). The measurements may be displayed live as the representative I/O is being executed and may also be logged for later review. The measurements may include … endurance attributes (e.g., write amplification factor etc.).” [0053] // ¶0048 // Fig. 6) – As shown in Bhimani Fig. 6, a “representative workload” comprising a plurality of I/O commands are passed to an SSD in order to benchmark performance of the SSD (see ¶0048), similar to how the Memory Device 110 of Mozak Fig. 1 is tested using a plurality of memory access transactions. Examiner accordingly considers the SSD of Bhimani as analogous to memory device 110 of Mozak Fig. 1. As taught in Bhimani Fig. 6, after the plurality of I/O commands are issued to the SSD, corresponding “measurements” including “write amplification factor” (i.e., “write statistics”) are displayed and are logged for review.
analyzing the data representing the write statistics to evaluate an endurance of the memory sub-system. (Bhimani, “The measurements may be displayed live … The measurements may include … endurance attributes (e.g. write amplification factor etc.)” [0053]) – As taught in Bhimani, write amplification factor enables the endurance of the SSD to be benchmarked
Mozak, Kanteti, and Bhimani are all considered analogous to the claimed invention because they all relate to the same field of testing memory devices using plural memory access commands received from an external host. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mozak and Kanteti with the teachings of Bhimani and realize a system whereby write statics are received after performance of a series of corresponding memory access operations. Doing enables improved memory device benchmarking to be performed using real-world I/O patterns with a traditional benchmarking tool, as disclosed in Bhimani ¶0054: “Accordingly, the above described embodiments of the present disclosure provide for systems and methods for testing storage devices using a representative I/O generator. Unlike previous systems for performing storage device benchmarking, the system is able to simulate real-world application I/O instead of the overly simplistic I/O of current benchmarking tools. Representative I/O allows for performing benchmarking that has the ease-of-use of using a traditional benchmarking tool while still providing the performance of an actual application workload. Additionally, the storage requirements are minimal when compared to using application traces.” [0054]
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Mozak (US 20140095946 A1) – Discloses a method of generating plural memory access commands to test a memory device (see Fig. 4)
Han et al. (US 20200218466 A1) – Discloses a method of mapping table initialization after a memory device wipe command received from a host (see Figs. 4A + 4B)
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/J.S.M./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133