Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Continuation filed on 1/09/2025.
Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/09/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Obvious-Type Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1, 8, 11, and 18 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 and 13-14 of U.S. Patent No. 11,861,218 (parent application s/n 17/981,817). Although the claims at issue are not identical, they are not patentably distinct from each other because Claims 1, 8, 11, and 18 of the instant Application, respectively contains every element of claims 1-2 and 13-14 of U.S. Patent No. 11,861,218 (parent application s/n 17/981,817), as listed below with underlined text showing differences between the two:
Claims
Instant Application
Claims
U.S. Patent No. 11,861,218 (parent application s/n 17/981,817)
Independent claim 1
A memory system connectable to a host, the host including a first buffer, the memory system comprising:
a nonvolatile memory, a data write operation to the nonvolatile memory being to be performed in a unit of a first size; and
a controller electrically connected to the nonvolatile memory and configured to:
after receiving, from the host, a first write command instructing to write first data of a second size from a first location of the first buffer of the host to the nonvolatile memory, the second size being smaller than the first size, wait for receiving a second write command without obtaining the first data from the first location of the first buffer of the host; and
in response to receiving, from the host, the second write command instructing to write second data of a third size from a second location of the first buffer of the host to the nonvolatile memory, a sum of the second size and the third size being larger than or equal to the first size,
transfer third data of the first size from the first buffer of the host to the nonvolatile memory, the third data including at least part of the first data and at least part of the second data; and
instruct the nonvolatile memory to write the third data.
Independent claim 1
A memory system connectable to a host, the host including a buffer, the memory system comprising:
a nonvolatile memory, a data write operation to the nonvolatile memory being to be performed in a unit of a first size; and
a controller electrically connected to the nonvolatile memory and configured to:
after receiving, from the host, a first write command instructing to write first data of a second size from the buffer of the host to the nonvolatile memory, the second size being smaller than the first size, wait for receiving a second write command without obtaining the first data from the buffer of the host; and
in response to receiving, from the host, the second write command instructing to write second data of a third size from the buffer of the host to the nonvolatile memory, a sum of the second size and the third size being larger than or equal to the first size,
transfer third data of the first size from the buffer of the host to the nonvolatile memory, the third data including at least a part of the first data and at least a part of the second data; and
instruct the nonvolatile memory to write the third data.
Analysis
Examiner points out that the instant claims are a variation of the claims seen in U.S. Patent No. 11,861,218 (parent application s/n 17/981,817). More specifically, the instant claims use a “first buffer”, “a first location of the first buffer” and “a second location of the first buffer” instead of just “buffer”, “from the buffer”, and “from the buffer” respectively in U.S. Patent No. 11,861,218 (parent application s/n 17/981,817). The implication of the instant claims is that there is possibly more than one buffer and that the first buffer has at least two locations / addresses compared with the more generic “buffer” with an unknown number of locations / addresses of U.S. Patent No. 11,861,218 (parent application s/n 17/981,817). As such, the instant claims include language that implies a narrower scope and thus would be anticipated by the already allowed claims of U.S. Patent No. 11,861,218 (parent application s/n 17/981,817).
Independent claim 11
A method of controlling a nonvolatile memory, a data write operation to the nonvolatile memory being to be performed in a unit of a first size, the method comprising:
after receiving, from a host that includes a first buffer, a first write command instructing to write first data of a second size from a first location of the first buffer of the host to the nonvolatile memory, the second size being smaller than the first size, waiting for receiving a second write command without obtaining the first data from the first location of the first buffer of the host; and
receiving, from the host, the second write command instructing to write second data of a third size from a second location of the first buffer of the host to the nonvolatile memory, a sum of the second size and the third size being larger than or equal to the first size;
in response to receiving the second write command,
transferring third data of the first size from the first buffer of the host to the nonvolatile memory, the third data including at least part of the first data and at least part of the second data; and
instructing the nonvolatile memory to write the third data.
Independent claim 13
A method of controlling a nonvolatile memory, a data write operation to the nonvolatile memory being to be performed in a unit of a first size, said method comprising:
after receiving, from a host that includes a buffer, a first write command instructing to write first data of a second size from the buffer of the host to the nonvolatile memory, the second size being smaller than the first size, waiting for receiving a second write command without obtaining the first data from the buffer of the host; and
in response to receiving, from the host, the second write command instructing to write second data of a third size from the buffer of the host to the nonvolatile memory, a sum of the second size and the third size being larger than or equal to the first size,
transferring third data of the first size from the buffer of the host to the nonvolatile memory, the third data including at least a part of the first data and at least a part of the second data; and
instructing the nonvolatile memory to write the third data.
Analysis
Examiner points out that the instant claims are a variation of the claims seen in U.S. Patent No. 11,861,218 (parent application s/n 17/981,817). More specifically, the instant claims use a “first buffer”, “a first location of the first buffer” and “a second location of the first buffer” instead of just “buffer”, “from the buffer”, and “from the buffer” respectively in U.S. Patent No. 11,861,218 (parent application s/n 17/981,817). The implication of the instant claims is that there is possibly more than one buffer and that the first buffer has at least two locations / addresses compared with the more generic “buffer” with an unknown number of locations / addresses of U.S. Patent No. 11,861,218 (parent application s/n 17/981,817). As such, the instant claims include language that implies a narrower scope and thus would be anticipated by the already allowed claims of U.S. Patent No. 11,861,218 (parent application s/n 17/981,817).
Likewise, the dependent claims of the above cited independent claims carry similar limitations to each other respectively.
Allowable Subject Matter
Claims 1-20 are indicated as allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art teaches systems and methods for implementing write commands between a host and nonvolatile memory using a controller and buffer / queue / cache including systems that implemented doing partial writes / multiple smaller writes to complete a whole write command request, however, the prior art does not fairly teach or suggest, individually or in combination, a memory system and method where a host including a first buffer does data write operations to a nonvolatile memory, the data write operations performed in a unit of a first size, and a controller where after receiving a first write command for writing of first data of a second size from the a first location of the first buffer to the nonvolatile memory with the second size being smaller than the first size, then the controller waits for receiving a second command without obtaining / fetching the first data from the first location, and in response to receiving a second write command for writing of second data of a third size from a second location of the first buffer to the nonvolatile memory, a sum of the second size and third size being larger than or equal to the first size, then the controller transfers third data of the first size from the first buffer of the host to the nonvolatile memory where the third data includes at least a part of the first data and at least a part of the second data, then instructing the nonvolatile memory to write the third data as claimed. Examiner finds that prior arts does not teach the first and second write commands where the first write command is received having a second size different than the first size (write size of the nonvolatile memory) and having a wait period after receiving the first write without receiving / fetching the write data, where in response to receiving a second write command having a third size and the sum of the second and third size being greater than the first size, then the controller will operate to transfer a third data in a first size that includes a part of first data and second data in the manner being claimed in the instant application. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nanjou et al. (US 2010/0199025) teaches a memory system where word lines are connected to memory cells of the memory to allow for read/write operations to the memory cell.
Suzuki et al. (US 8,717,842) teaches a DRAM memory system with multiple ports, wherein word lines and bit lines are associated with the ports to allow for read/write operations to memory.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183