DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending, of which all pending claims are rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hao et al. (US 2017/0131351), in view of Kim et al. (US 2024/0338289 A1), (hereinafter Hao-Kim).
Regarding claim 1, Hao teaches, an integrated circuit (IC) (Hao: “The present invention is directed to multi-core integrated circuits and, more particularly, to testing a multi-core integrated circuit…” [0001]), comprising:
a plurality of cores that are identical (Hao: “FIG. 2 illustrates a multi-core IC 200 in accordance with an embodiment of the present invention. The IC 200 comprises a set of nominally similar cores CORE1 to COREn.” [0011]), wherein each core of the plurality of cores is configured to generate a respective test output ….. (Hao: ‘test data outputs TDO1 to TDOm’ [Fig.2]); and
a diagnostic circuit coupled to the plurality of cores (Hao: ‘diagnosis modules 208_1 to 208_m’ [Fig.2] & [0015]), wherein the diagnostic circuit is configured to:
receive (i) a plurality of test outputs that include the test output of each of the plurality of cores (Hao: ‘the diagnostic modules 208_1 to 208_m receives test outputs from each of the plurality of cores [Fig.2] & [0015-0016 ]) and (ii) a default selection signal, wherein the default selection signal indicates one of the plurality of test outputs as a default test output (Hao: ‘the expected response signals’ [Fig.2] & [0014]);
identify, based on the plurality of test outputs and the default test output, a defective set of cores of the plurality of cores (Hao: “However, with the present invention the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014]); and
output a set of defective outputs associated with the defective set of defective cores as a set of failure logs (Hao: “….the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014]);.
Hao does not explicitly disclose, ….test output based on a plurality of test patterns;
However, Kim teaches in an analogous art, “[0112] The test pattern generator 121b is configured to generate test patterns used to test each core of the chip, and the test patterns are designed for detecting any faults occurring within the cores. generated in various ways, including pseudo random patterns, patterns generated according to a specific predetermined rule, or combinations thereof. The test pattern generator is configured to generate test patterns according to the test scheduling. [0113] …..the response monitor 121c is configured to detect any discrepancy by inputting the generated test patterns into each of the multiple cores and comparing a response from each of the multiple cores with an expected response. And the response monitor is further configured to determine that no fault is detected in a core, if a detected fault rate for the core is below a predetermined fault rate, or even if a fault is detected in the core as long as it is possible for the core to correctly execute predetermined tasks functionally, and enable predetermined tasks to be performed with the core in the harvesting of performance.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hao’s teachings of ‘testing multi-core IC’ with Kim’s teaching of ‘fault detection in a core’ to provide a method and device for performing performance harvesting, where multiple cores are embedded in a matrix structure and configured to perform their operations independently, for allowing the remaining cores to independently produce results of operations by harvesting their respective performances, and exclude the defected cores from the operations. By doing so, to enhance yields of the manufacturing process of a chip embedding multiple cores in a matrix form, and to extend the lifetime of the chip during its usage.
Regarding claim 2, Hao-Kim teaches, the IC of claim 1, wherein the plurality of test patterns are associated with testing of the plurality of cores (Kim: “….the response monitor 121c is configured to detect any discrepancy by inputting the generated test patterns into each of the multiple cores and comparing a response from each of the multiple cores with an expected response.” [0113]).
Regarding claim 3, Hao-Kim teaches, the IC of claim 1, wherein the diagnostic circuit comprises a comparator circuit, and wherein the comparator circuit is configured to: receive the plurality of test outputs and the default selection signal; compare each of the plurality of test outputs with the default test output; and generate a plurality of status bits based on the comparison, wherein the defective set of cores is identified based on the plurality of status bits (Hao: “…the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014]).
Regarding claim 4, Hao-Kim teaches, the IC of claim 3, wherein the comparator circuit comprises a default multiplexer configured to: receive (i) the plurality of test outputs and (ii) the default selection signal; and output one of the plurality of test outputs as the default test output based on the default selection signal (Hao: “…..The multiplexers 206_1 to 206_m select the first or second combined TDO signals TDO1′ to TDOm′ or TDO1″ to TDOm″ and provide the selected combined TDO signals to the corresponding TDO pads TDO CHAIN1 to TDO CHAINm.” [0018]; ‘the expected response signals’ [Fig.2] & [0014]; “….the ATE 120 comparing the response signals from the selected core with the corresponding expected response signals.” [0021]).
Regarding claim 5, Hao-Kim teaches, the IC of claim 4, wherein the comparator circuit further comprises a plurality of exclusive- OR (XOR) gates coupled to the default multiplexer, and wherein each XOR gate of the plurality of XOR gates is configured to: receive (i) a corresponding test output of the plurality of test outputs and (ii) the default test output; and output one of a plurality of XOR signals based on the corresponding test output and the default test output (Hao: “….the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014]).
Regarding claim 6, Hao-Kim teaches, the IC of claim 5, wherein the comparator circuit further comprises a first plurality of AND gates, wherein each AND gate of the first plurality of AND gates is coupled to a corresponding XOR gate of the plurality of XOR gates, and wherein each AND gate of the first plurality of AND gates is configured to: receive a corresponding XOR signal of the plurality of XOR signals and a first enable signal; and output one of a first plurality of AND signals based on the corresponding XOR signal and the first enable signal (Hao: “….the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014,0020-0021]; ‘Hao teaches comparing the combined TDO signals with the corresponding expected response signals to determine pass or fail for the IC and then performing a diagnosis process on the IC to identify a defective core [0020-0021]. With the teaching of Hao, it would have been obvious, well known, and design choice for a person ordinary skill in the art before the effective filing date of the claimed invention that a compare and/or diagnostic circuit may include a number of different types logic gates (e.g. AND, OR, XOR etc.), signals, and/or status bits’).
Regarding claim 7, Hao-Kim teaches, the IC of claim 6, wherein the comparator circuit further comprises a plurality of memory circuits, wherein each memory circuit of the plurality of memory circuits is coupled to a corresponding AND gate of the first plurality of AND gates, and wherein each memory circuit of the plurality of memory circuits is configured to: receive a corresponding AND signal of the first plurality of AND signals and a clock signal as inputs; generate a corresponding status bit of the plurality of status bits based on the inputs; and output the generated status bit (Hao: “….the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014,0020-0021]; ‘Hao teaches comparing the combined TDO signals with the corresponding expected response signals to determine pass or fail for the IC and then performing a diagnosis process on the IC to identify a defective core [0020-0021]. With the teaching of Hao, it would have been obvious, well known, and design choice for a person ordinary skill in the art before the effective filing date of the claimed invention that a compare and/or diagnostic circuit may include a number of different types logic gates (e.g. AND, OR, XOR etc.), signals, and/or status bits’).
Regarding claim 8, Hao-Kim teaches, the IC of claim 3, wherein the diagnostic circuit further comprises a selection circuit coupled to the comparator circuit, and wherein the selection circuit is configured to: receive the plurality of status bits, the plurality of test outputs, the default test output, and a mode signal, wherein the identification of the defective set of cores is based on the plurality of status bits, and wherein the mode signal is generated based on the plurality of status bits; and output one of (i) in a set of iterations, the set of defective outputs and a set of core identifiers indicative of the defective set of cores when the mode signal indicates that the selection circuit operates in a normal mode, wherein in each iteration of the set of iterations, a corresponding defective output of the set of defective outputs and a corresponding core identifier of the set of core identifiers is outputted, and (ii) a defective output that corresponds to the default test output and a core identifier that is indicative of the core associated with the default test output when the mode signal indicates that the selection circuit operates in a default mode, wherein the set of defective outputs includes the default test output (Hao: ‘the iterative diagnosis process of identifying defective core(s)’ [0014, 0021-0022]).
Regarding claim 9, Hao-Kim teaches, the IC of claim 8, further comprising a plurality of output pads coupled to the selection circuit, wherein the plurality of output pads comprises a first set of output pads and a second set of output pads, and wherein in each iteration of the set of iterations,(i) the first set of output pads is configured to: receive the corresponding defective output of the set of defective outputs; and provide the corresponding defective output as a failure log of the set of failure logs, from the IC to a test system; and (ii) the second set of output pads is configured to: receive the corresponding core identifier associated with the corresponding defective output; and provide the corresponding core identifier from the IC to the test system (Hao: ‘test data input and output pads’ [0012-0013]).
Regarding claim 10, Hao-Kim teaches, the IC of claim 8, wherein the selection circuit comprises a control circuit, and wherein when the selection circuit operates in the normal mode, the control circuit is configured to: output,(i) in a first iteration of the set of iterations, a plurality of logic signals associated with the plurality of cores based on the plurality of status bits, wherein each of the plurality of logic signals is de-asserted, and(ii) in each remaining iteration of the set of iterations, the plurality of logic signals such that a logic signal associated with a core identifier of the set of core identifiers outputted in a preceding iteration of the set of iterations is asserted (Hao: ‘the iterative diagnosis process of identifying defective core(s)’ [0014, 0021-0022]).
Regarding claim 11, Hao-Kim teaches, the IC of claim 10, wherein each status bit of the plurality of status bits is associated with a core of the plurality of cores, wherein a value of a status bit of the plurality of status bits being one indicates that the core associated with the corresponding status bit is defective, and wherein the control circuit is further configured to provide, to a test system,(i) in the first iteration, a core identifier of the set of core identifiers associated with a least significant bit of the plurality of status bits, wherein the least significant bit is asserted, and (ii) in each remaining iteration of the set of iterations, a core identifier of the set of core identifiers associated with a status bit that (i) is asserted and (ii) succeeds the status bit associated with the core identifier outputted in the preceding iteration (Hao: ‘the iterative diagnosis process of identifying defective core(s)’ [0014, 0021-0022]).
Regarding claim 12, Hao-Kim teaches, the IC of claim 11, wherein the selection circuit further comprises: a plurality of inverters coupled to the control circuit, wherein the plurality of inverters is associated with the plurality of cores, and wherein when the selection circuit operates in the normal mode, each inverter of the plurality of inverters is configured to: receive a logic signal of the plurality of logic signals; invert the logic signal; and output one of a plurality of inverted logic signals; and a second plurality of AND gates coupled to the plurality of inverters, wherein the second plurality of AND gates are associated with the plurality of cores, and wherein each AND gate of the second plurality of AND gates is configured to: receive a corresponding status bit of the plurality of status bits and a corresponding inverted logic signal of the plurality of inverted logic signals as inputs; and output one of a second plurality of AND signals based on the corresponding status bit and the corresponding inverted logic signal (Hao: ‘the steps of identifying defective core(s)’ [0014, 0021]).
Regarding claim 13, Hao-Kim teaches, the IC of claim 12, wherein the selection circuit further comprises a plurality of control multiplexers coupled to the second plurality of AND gates, wherein the plurality of control multiplexers is associated with the plurality of cores, and wherein when the selection circuit operates in the normal mode, each control multiplexer of the plurality of control multiplexers is configured to: receive a corresponding AND signal of the second plurality of AND signals, a second enable signal, and a select signal; and output one of a plurality of control signals based on the select signal (Hao: ‘the multiplexers’ [0016-0018]).
Regarding claim 14, Hao-Kim teaches, the IC of claim 13, wherein the selection circuit further comprises a plurality of expose multiplexers coupled to the plurality of control multiplexers and the plurality of cores, wherein when the selection circuit operates in the normal mode, a default expose multiplexer of the plurality of expose multiplexers is configured to: receive the default test output, a corresponding test output of the plurality of test outputs, and a corresponding control signal of the plurality of control signals; and output one of the default test output and the corresponding test output as the set of failure logs based on the corresponding control signal, wherein each remaining expose multiplexer of the plurality of expose multiplexers is coupled to a preceding expose multiplexer of the plurality of expose multiplexers, wherein each remaining expose multiplexer of the plurality of expose multiplexers is configured to: receive a corresponding test output of the plurality of test outputs, a corresponding control signal of the plurality of control signals, and an output of the preceding expose multiplexer; and output one of the corresponding test output and the output of the preceding expose multiplexer based on the corresponding control signal, and wherein a first expose multiplexer of the plurality of expose multiplexers, outputs in a corresponding iteration of the set of iterations, a corresponding defective output of the set of defective outputs(Hao: ‘the multiplexers’ [0016-0018]).
Regarding claim 15, Hao-Kim teaches, the IC of claim 8, wherein the selection circuit comprises a control circuit, wherein when the selection circuit operates in the default mode, the control circuit is configured to output a plurality of logic signals associated with the plurality of cores based on the plurality of status bits, and wherein each of the plurality of logic signals is asserted (Hao: ‘the iterative diagnosis process of identifying defective core(s)’ [0014, 0021-0022]).
Regarding claim 16, Hao-Kim teaches, the IC of claim 15, wherein the control circuit is further configured to provide a core identifier of the set of core identifiers that is indicative of the core associated with the default test output to a test system (Hao: ‘the iterative diagnosis process for identification defective core(s)’ [0014, 0021-0022]).
Regarding claim 17, Hao-Kim teaches, the IC of claim 16, wherein the selection circuit further comprises: a plurality of inverters coupled to the control circuit, wherein the plurality of inverters is associated with the plurality of cores, and wherein when the selection circuit operates in the default mode, each inverter of the plurality of inverters is configured to: receive a logic signal of the plurality of logic signals; invert the logic signal; and output one of a plurality of inverted logic signals; and a second plurality of AND gates coupled to the plurality of inverters, wherein the second plurality of AND gates are associated with the plurality of cores, and wherein each AND gate of the second plurality of AND gates is configured to: receive a corresponding status bit of the plurality of status bits and a corresponding inverted logic signal of the plurality of inverted logic signals; and output one of a second plurality of AND signals based on the corresponding status bit and the corresponding inverted logic signal (Hao: “….the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014,0020-0021]; ‘Hao teaches comparing the combined TDO signals with the corresponding expected response signals to determine pass or fail for the IC and then performing a diagnosis process on the IC to identify a defective core [0020-0021]. With the teaching of Hao, it would have been obvious, well known, and design choice for a person ordinary skill in the art before the effective filing date of the claimed invention that a compare and/or diagnostic circuit may include a number of different types logic gates (e.g. AND, OR, XOR etc.), signals, and/or status bits’).
Regarding claim 18, Hao-Kim teaches, the IC of The IC of wherein the selection circuit further comprises a plurality of control multiplexers coupled to the second plurality of AND gates, wherein the plurality of control multiplexers is associated with the plurality of cores, and wherein when the selection circuit operates in the default mode, each control multiplexer of the plurality of control multiplexers is configured to: receive a corresponding AND signal of the second plurality of AND signals, a second enable signal, and a select signal; and output one of a plurality of control signals based on the select signal (Hao: “….the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014,0020-0021]; ‘Hao teaches comparing the combined TDO signals with the corresponding expected response signals to determine pass or fail for the IC and then performing a diagnosis process on the IC to identify a defective core [0020-0021]. With the teaching of Hao, it would have been obvious, well known, and design choice for a person ordinary skill in the art before the effective filing date of the claimed invention that a compare and/or diagnostic circuit may include a number of different types logic gates (e.g. AND, OR, XOR etc.), signals, and/or status bits’).
Regarding claim 19, Hao-Kim teaches, the IC of claim 18, wherein the selection circuit further comprises a plurality of expose multiplexers coupled to the plurality of control multiplexers and the plurality of cores, wherein when the selection circuit operates in the default mode, a default expose multiplexer of the plurality of expose multiplexers is configured to: receive the default test output, a corresponding test output of the plurality of test outputs, and a corresponding control signal of the plurality of control signals; and output one of the default test output and the corresponding test output based on the corresponding control signal, wherein each remaining expose multiplexer of the plurality of expose multiplexers is coupled to a preceding expose multiplexer of the plurality of expose multiplexers, wherein each remaining expose multiplexer of the plurality of expose multiplexers is configured to: receive a corresponding test output of the plurality of test outputs, a corresponding control signal of the plurality of control signals, and an output of the preceding expose multiplexer; and output one of the corresponding test output and the output of the preceding expose multiplexer based on the corresponding control signal, and wherein a first expose multiplexer of the plurality of expose multiplexers, outputs the defective output associated with the default test output (Hao: “….the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014,0020-0021]; ‘Hao teaches comparing the combined TDO signals with the corresponding expected response signals to determine pass or fail for the IC and then performing a diagnosis process on the IC to identify a defective core [0020-0021]. With the teaching of Hao, it would have been obvious, well known, and design choice for a person ordinary skill in the art before the effective filing date of the claimed invention that a compare and/or diagnostic circuit may include a number of different types logic gates (e.g. AND, OR, XOR etc.), signals including selection signals, and/or status bits’).
Regarding claim 20, Hao teaches, a diagnostic method, comprising:
generating, by each core of a plurality of cores of an integrated circuit (IC) (Hao: “The present invention is directed to multi-core integrated circuits and, more particularly, to testing a multi-core integrated circuit…” [0001]), a respective test output ….. (Hao: ‘test data outputs TDO1 to TDOm’ [Fig.2]), wherein the plurality of cores are identical (Hao: “FIG. 2 illustrates a multi-core IC 200 in accordance with an embodiment of the present invention. The IC 200 comprises a set of nominally similar cores CORE1 to COREn.” [0011]);
receiving, by a diagnostic circuit of the IC (Hao: ‘diagnosis modules 208_1 to 208_m’ [Fig.2] & [0015]), (i) a plurality of test outputs that include the test output of each of the plurality of cores (Hao: ‘the diagnostic modules 208_1 to 208_m receives test outputs from each of the plurality of cores [Fig.2] & [0015-0016 ]) and (ii) a default selection signal, wherein the default selection signal indicates one of the plurality of test outputs as a default test output (Hao: ‘the expected response signals’ [Fig.2] & [0014]);
identifying, by the diagnostic circuit, based on the plurality of test outputs and the default test output, a defective set of cores of the plurality of cores (Hao: “However, with the present invention the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014]); and
outputting, by the diagnostic circuit, a set of defective outputs associated with the defective set of cores as a set of failure logs (Hao: “….the combined TDO signals TDO1 to TDOm are available to the ATE 120, which compares them with the expected response signals in detail and stores the results of the comparison in a failure log, useful in diagnosing the defects and identifying the defective core or cores.” [0014]).
Hao does not explicitly disclose, ….test output based on a plurality of test patterns;
However, Kim teaches in an analogous art, “[0112] The test pattern generator 121b is configured to generate test patterns used to test each core of the chip, and the test patterns are designed for detecting any faults occurring within the cores. generated in various ways, including pseudo random patterns, patterns generated according to a specific predetermined rule, or combinations thereof. The test pattern generator is configured to generate test patterns according to the test scheduling. [0113] …..the response monitor 121c is configured to detect any discrepancy by inputting the generated test patterns into each of the multiple cores and comparing a response from each of the multiple cores with an expected response. And the response monitor is further configured to determine that no fault is detected in a core, if a detected fault rate for the core is below a predetermined fault rate, or even if a fault is detected in the core as long as it is possible for the core to correctly execute predetermined tasks functionally, and enable predetermined tasks to be performed with the core in the harvesting of performance.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Hao’s teachings of ‘testing multi-core IC’ with Kim’s teaching of ‘fault detection in a core’ to provide a method and device for performing performance harvesting, where multiple cores are embedded in a matrix structure and configured to perform their operations independently, for allowing the remaining cores to independently produce results of operations by harvesting their respective performances, and exclude the defected cores from the operations. By doing so, to enhance yields of the manufacturing process of a chip embedding multiple cores in a matrix form, and to extend the lifetime of the chip during its usage.
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
Seuring (US 2008/0148117 A1) teaches an integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.
When amending the claims, Applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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