DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Claims, specification, and remarks filed on 6/12/2026.
Withdrawn objections and rejections
The specification objections have been withdrawn due to amendment.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-9, 12-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. 2022/0066736), in view of Nam (U.S. 2020/0285605).
As per claim 1:
Chen disclosed a systolic array comprising:
a plurality of sub processing element (PE) arrays, wherein each of the plurality of sub PE arrays is configured to receive an input signal and to generate an output signal based on the received input signal (Chen: Figure 2 elements U11-U44, paragraph 22-25)(A given column or row of the matrix device array, including the MAC and L1 elements, reads upon a sub PE array. Each of the individual MAC elements receives weights and input data. Each of the L1 registers output the generated MAC result (i.e. output signal).); and
wherein an ODP circuit of the plurality of ODP circuits receives the output signal of a previous sub PE array of the plurality of sub PE arrays (Chen: Figures 2 and 4 elements U11-U44, S410, and S440, paragraph 25, 33-34, and 40-41)(A given column or row of L2 registers (i.e. ODP circuits) receives MAC results from a given column or row of L1 registers.), wherein the ODP circuit provides the output signal to a next sub PE array of the plurality of sub PE arrays in the first mode (Chen: Figures 2 and 4 elements U11-U44, S410, and S440, paragraph 25, 33-34, and 40-41)(A given column or row of L2 registers (i.e. ODP circuits) outputs MAC results to MAC units in adjacent columns/rows in a first and second mode. For example, the left-most column of MAC and L1 elements output MAC results to the left-most L2 registers. In the second mode of Chen (i.e. first mode), the L2 registers outputs MAC results along rows to the second to top row of MAC and L1 elements (i.e. next sub PE array). In the first mode of Chen (i.e. first mode), the L2 registers outputs MAC results along columns to the second to left column of MAC and L1 elements (i.e. next sub PE array).).).
Chen failed to teach a plurality of output direct path (ODP) circuits configured to selectively operate in either a first mode or in a second mode and wherein the ODP circuit outputs the output signal without providing the output signal to the next sub PE array in the second mode.
However, Nam combined with Chen disclosed a plurality of output direct path (ODP) circuits configured to selectively operate in either a first mode or in a second mode (Nam: Figure 1 elements R11_4 to R33_4 and MUX11-MUX33, paragraphs 21-26)(Chen: Figures 2 and 4 elements U11-U44, S410, and S440, paragraph 25, 33-34, and 40-41)(Chen disclosed a given column or row of L2 registers (i.e. ODP circuits) outputting MAC results to MAC units in adjacent columns/rows in a first and second mode. Chen disclosed the L2 registers both receiving an L1 output and an L2 output from a previous row/column. Nam disclosed a multiplexer to select between a previous result and an accumulated result. The combination implements the multiplexer in each sub-array element (i.e. u11-u44) to select storing in each L2 register either an L1 output result or a prior L2 register result. Outputting L1 results from the L2 register is done in a first mode and outputting prior L2 register results is done in a second mode.),
wherein the ODP circuit outputs the output signal without providing the output signal to the next sub PE array in the second mode (Nam: Figure 1 elements R11_4 to R33_4 and MUX11-MUX33, paragraphs 21-26)(Chen: Figures 2 and 4 elements U11-U44, S410, and S440, paragraph 25, 33-34, and 40-41)(The combination implements the multiplexer in each sub-array element (i.e. u11-u44) to select storing in each L2 register either an L1 output result or a prior L2 register result. Outputting L1 results from the L2 register is done in a first mode and outputting prior L2 register results is done in a second mode. In the second mode, the L1 result (i.e. output signal) isn’t provided to the next sub-array element.).
Chen disclosed an option for processing results to be passed through sub-array PEs for output, but doesn’t provide a specific mechanism for selection. One of ordinary skill in the art would have been motivated by this lack of teaching to find the Nam reference that uses multiplexers to selectively output PE element results. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the PE multiplexers of Nam within each sub-array element of Chen to fill in the missing selection mechanism.
As per claim 2:
Chen and Nam disclosed the systolic array of claim 1, wherein each ODP circuit of the plurality of ODP circuits is disposed between two consecutive sub PE arrays of the plurality of sub PE arrays (Chen: Figures 2 and 4 elements U11-U44, S410, and S440, paragraph 25, 33-34, and 40-41)(A given column or row of L2 registers (i.e. ODP circuits) receives MAC results from a given column or row of L1 registers. For example, the columns of L2 registers, excluding the right-most column, are all between columns of MAC and L1 register elements.).
As per claim 5:
Chen and Nam disclosed the systolic array of claim 1, wherein the ODP circuit outputs the output signal of the previous sub PE array to a restoration circuit in the second mode (Chen: Figures 1-2 and 4 elements 30, 200, U11-U44, S410, and S440, paragraphs 18, 25, 33-34, and 40-41)(The broadest reasonable interpretation of restoration circuit is a circuit that outputs a final matrix result. A given column or row of L2 registers (i.e. ODP circuits) outputs MAC results to MAC units in adjacent columns/rows in a first and second mode. For example, the left-most column of MAC and L1 elements output MAC results to the left-most L2 registers. In the first mode of Chen (i.e. second mode), the L2 registers outputs MAC results along columns to the second from top row of MAC and L1 elements. The bottom row of L2 registers output the final matrix result to memory.).
As per claim 6:
Chen and Nam disclosed the systolic array of claim 1, wherein the ODP circuit comprises a sub output buffer and one or more multiplexers, wherein the sub output buffer is configured to receive the output signal of the previous sub PE array as input (Nam: Figure 1 elements R11_4 to R33_4 and MUX11-MUX33, paragraphs 21-26)(Chen: Figures 2 and 4 elements U11-U44, S410, and S440, paragraph 25, 33-34, and 40-41)( The combination implements the multiplexer in each sub-array element (i.e. u11-u44) to select storing in each L2 register either an L1 output result or a prior L2 register result. A given column or row of L2 registers (i.e. ODP circuit collectively, output buffer individually) receives MAC results from previous MAC units and L1 registers in adjacent columns/rows.), and wherein the one or more multiplexers are each connected to the sub output buffer (Nam: Figure 1 elements R11_4 to R33_4 and MUX11-MUX33, paragraphs 21-26)(Chen: Figures 2 and 4 elements U11-U44, S410, and S440, paragraph 25, 33-34, and 40-41)(The combination implements the multiplexer in each sub-array element (i.e. u11-u44) to select storing in each L2 register either an L1 output result or a prior L2 register result. A given column or row of L2 registers (i.e. ODP circuit collectively, output buffer individually) receives MAC results from both L1 and L2 registers. The added multiplexers are connected to the L2 output buffer register.).
As per claim 7:
Chen and Nam disclosed the systolic array of claim 6, wherein:
the one or more multiplexers provide the output signal of the previous sub PE array to the next sub PE array in the first mode (Nam: Figure 1 elements R11_4 to R33_4 and MUX11-MUX33, paragraphs 21-26)(Chen: Figures 2 and 4 elements U11-U44, S410, and S440, paragraph 25, 33-34, and 40-41)(Chen disclosed a given column or row of L2 registers (i.e. ODP circuits) outputting MAC results to MAC units in adjacent columns/rows in a first and second mode. Chen disclosed the L2 registers both receiving an L1 output and an L2 output from a previous row/column. Nam disclosed a multiplexer to select between a previous result and an accumulated result. The combination implements the multiplexer in each sub-array element (i.e. u11-u44) to select storing in each L2 register either an L1 output result or a prior L2 register result. Outputting L1 results from the L2 register is done in a first mode, which sends it to the next row/column sub-array.) and the sub output buffer outputs the output signal of the previous sub PE array in the second mode (Nam: Figure 1 elements R11_4 to R33_4 and MUX11-MUX33, paragraphs 21-26)(Chen: Figures 2 and 4 elements U11-U44, S410, and S440, paragraph 25, 33-34, and 40-41)(The combination implements the multiplexer in each sub-array element (i.e. u11-u44) to select storing in each L2 register either an L1 output result or a prior L2 register result. Outputting L1 results from the L2 register is done in a first mode and outputting prior L2 register results is done in a second mode. In the second mode, a previous L2 result is output.).
As per claim 8:
Claim 8 essentially recites the same limitations of claim 1. Therefore, claim 8 is rejected for the same reasons as claim 1.
As per claim 9:
The additional limitation(s) of claim 9 basically recite the additional limitation(s) of claim 2. Therefore, claim 9 is rejected for the same reason(s) as claim 2.
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 5. Therefore, claim 12 is rejected for the same reason(s) as claim 5.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 6. Therefore, claim 13 is rejected for the same reason(s) as claim 6.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claims 5 and 7. Therefore, claim 14 is rejected for the same reason(s) as claims 5 and 7.
As per claim 15:
Claim 15 essentially recites the same limitations of claim 1. Claim 15 additionally recites the following limitations:
A processing circuit comprising a systolic array (Chen: Figure 2, paragraph 3).
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 2. Therefore, claim 16 is rejected for the same reason(s) as claim 2.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 5. Therefore, claim 19 is rejected for the same reason(s) as claim 5.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 6. Therefore, claim 20 is rejected for the same reason(s) as claim 6.
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. 2022/0066736), in view of Nam (U.S. 2020/0285605), further in view of Gunnam et al. (U.S. 2021/0191733).
As per claim 3:
Chen and Nam disclosed the systolic array of claim 1.
Chen and Nam failed to teach wherein a first time period for receiving a first input signal at a first sub PE array of the plurality of sub PE arrays overlaps a second time period for receiving a second input signal at a second sub PE array of the plurality of sub PE arrays.
However, Gunnam combined with Chen and Nam disclosed wherein a first time period for receiving a first input signal at a first sub PE array of the plurality of sub PE arrays overlaps a second time period for receiving a second input signal at a second sub PE array of the plurality of sub PE arrays (Gunnam: Figure 8A-H element 800, paragraphs 60-63)(Chen: Figure 2, paragraphs 22-25)(Chen disclosed broadcasting inputs and weights to MAC elements. Gunnam disclosed synchronizing the feeding of inputs and weights along clock cycles to a systolic array. This allows for overlaps in PE elements of the systolic array receiving different inputs at different times. For example, Figures 8C-H show various elements receiving different inputs during a same clock cycle. The combination results in Chen being able to feed inputs and weights to MAC elements in the same manner.).
The advantage of the synchronized feeding of inputs and weights is that individual processing elements can complete a single matrix element convolution, which reduces complexity in calculating the final matrix output. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the synchronized feeding of inputs and weights from Gunnam into the system of Chen for the above advantage.
As per claim 10:
The additional limitation(s) of claim 10 basically recite the additional limitation(s) of claim 3. Therefore, claim 10 is rejected for the same reason(s) as claim 3.
As per claim 17:
The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claim 3. Therefore, claim 17 is rejected for the same reason(s) as claim 3.
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. 2022/0066736), in view of Nam (U.S. 2020/0285605), further in view of Cho (U.S. 2022/0222315) and Narayanamoorthy et al. (U.S. 2020/0265107).
As per claim 4:
Chen and Nam disclosed the systolic array of claim 1.
Chen and Nam failed to teach wherein the plurality of sub PE arrays is preloaded with weight values corresponding to a weight matrix in the first mode and corresponding to a condensed weight matrix in the second mode.
However, Cho combined with Chen and Nam disclosed wherein the plurality of sub PE arrays is preloaded with weight values corresponding to a weight matrix in the first mode (Cho: Figures 1-3 elements 100, 130 and S110, paragraphs 42, 51-52, and 57)(Chen: Figures 2 and 4 elements U11-U44, S400, S410, and S440, paragraph 25, 33-34, and 40-41)(Cho disclosed preloading weight values for general matrix and convolution operations. The combination implements the weight registers and preloading step of Cho into the system of Chen. The combination allows for preloading the set of weight registers for use in a given output mode of Chen.).
The advantage of preloading weight data into matrix MAC processing elements is that data input feeding times can be reduced when weight data is reused by subsequent processing operations. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the preloading methods of Cho into the system of Chen for the above advantage.
Chen, Nam, and Cho failed to teach wherein the plurality of sub PE arrays corresponding to a condensed weight matrix in the second mode.
However, Narayanamoorthy combined with Chen, Nam, and Cho disclosed wherein the plurality of sub PE arrays corresponding to a condensed weight matrix in the second mode (Narayanamoorthy: Figures 2A-4, paragraphs 46-63)(Chen: Figures 2 and 4 elements U11-U44, S400, S410, and S440, paragraph 25, 33-34, and 40-41)(Narayanamoorthy disclosed sparse dense matrix operations that only require a subset of processing elements to calculate a matrix result. The combination implements sparse dense matrix operations and corresponding controls into the system of Chen. The combination allows for sparse matrix processing of weights in a given output mode of Chen.).
The advantage of performing sparse matrix operations is that fewer MAC units are needed for calculating a result, which allows for the advantage of reduced power usage when combined with power/clock gating unused processing elements for such operations. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the sparse matrix processing of Narayanamoorthy into the system of Chen for the above advantage.
As per claim 11:
The additional limitation(s) of claim 11 basically recite the additional limitation(s) of claim 4. Therefore, claim 11 is rejected for the same reason(s) as claim 4.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 4. Therefore, claim 18 is rejected for the same reason(s) as claim 4.
Response to Arguments
The arguments presented by Applicant in the response, received on 6/12/2026 are partially considered persuasive.
Applicant argues for claims 1, 8, and 15:
“First, the pending claims recite a systolic array comprising a plurality of sub PE arrays and a plurality of ODP circuits, wherein, in the first mode, an ODP circuit provides the output signal of a previous sub PE array to a next sub PE array, thereby chaining the sub PE arrays together to collectively function as a single, larger systolic array. Chen does not teach or suggest this architecture. Chen describes a monolithic 4x4 unit circuit array in which each individual unit circuit (ul 1-u44) contains a MAC, an L1 register, and an L2 register. The L2 registers of Chen's unit circuits are not "ODP circuits" that route signals between distinct "sub PE arrays"; they are simply storage registers within each individual unit circuit. Critically, Chen contains no "sub PE arrays" at all. A column or row of individual unit circuits and their associated L2 registers does not constitute a "sub PE array" in any meaningful sense, because there is no grouping of PEs into distinct sub-arrays that can each independently perform MAC operations. The Office Action's mapping conflates a single-element register (L2) with a circuit (ODP) whose entire purpose is to mediate signal flow between distinct, independently-operable PE sub-arrays, which is a structural distinction the claims explicitly require and that Chen nowhere describes. Thus, at least for these reasons, the pending claims are novel over Chen.”
This argument is not found to be persuasive for the following reason. The claimed limitation only requires sub PE arrays that receive inputs and generate outputs based on the input signal. A given column/row of the matrix multiplication device clearly reads upon this broadly claimed element. For example, u11, u21, u31, and u41 all receive weights and matrix A elements while providing a MAC output. Thus, reading upon the claimed limitation.
Applicant argues for claims 1, 8, and 15:
“Second, the functional behavior the claims require of the ODP circuit is entirely absent from Chen. In the first mode of the pending claims, the ODP circuit passes the output of one sub PE array into the next sub PE array so that all sub PE arrays operate as one unified systolic array. In the second mode, the ODP circuit instead diverts that output signal outward (e.g., to a restoration circuit), enabling each sub PE array to operate independently. This mode-switchable, intra-array chaining/un-chaining function has no counterpart in Chen. Chen's two output modes address only the direction in which accumulated results leave the array, either column-wise (to a memory for use in a subsequent matrix multiplication) or row-wise (to a downstream circuit for a vector operation), for the purpose of avoiding a separate matrix-transpose operation. In neither of Chen's output modes does any register "provide" a result to a different, adjacent group of processing elements within the same device so as to form a larger chained array. The Office Action's own analysis acknowledges this distinction by swapping Chen's labeled "first mode" and "second mode" to force a mapping onto the claims, a maneuver that itself reveals that Chen's modes are not functionally equivalent to those recited in the claims. Thus, at least for these reasons, the pending claims are novel over Chen.
In particular, the amended independent claims expressly distinguish the claimed mode switching from Chen's output-direction switching. In the first mode, the ODP circuit provides the output of a previous sub PE array to a next sub PE array so that the plurality of sub PE arrays can operate in a chained manner as a single larger systolic array. In contrast, in the second mode, the ODP circuit outputs the output of the previous sub PE array without providing the output to the next sub PE array, thereby allowing each sub PE array to independently generate an operation result. Thus, Chen's alleged mode switching, which merely changes the direction in which accumulated results are transferred between the row direction and the column direction, does not disclose or suggest changing whether the sub PE arrays are connected to each other as claimed.”
This argument is found to be persuasive for the following reason. The examiner agrees that Chen failed to teach the newly claimed limitation. However, a new ground of rejection has been applied based on the amendment.
Applicant argues for claims 6, 13, and 20:
“The claimed ODP circuit comprises a specific structural combination: (1) a sub output buffer configured to receive the output signal of the previous sub PE array as input, and (2) one or more multiplexers each connected to the sub output buffer, wherein in the first mode the multiplexers route the output signal to the next sub PE array, and in the second mode the sub output buffer directly outputs the output signal externally (e.g., to a restoration circuit per claims 7 and 14). This two-mode switching architecture, where the ODP circuit either propagates partial sums downstream to continue a cascaded computation, or exits the array entirely to a restoration circuit, is a critical feature absent from Chen. In Chen, the L2 registers always route MAC results to adjacent MAC units in both operational modes; Chen nowhere teaches or suggests an L2 register (or any analogous element) that can bypass the cascaded array and deliver its output signal directly to a restoration circuit. The Official Notice taken by the Office Action establishes only that multiplexers are generically useful for selecting multiple inputs, but provides no teaching or motivation to configure any such multiplexer to enable a fundamentally different output path that escapes the array in the second mode as claimed. Adding a conventional multiplexer to Chen's L2 registers would at most allow selection among internal array inputs, not the distinct, mode-selectable external output path recited in the claims. Because neither Chen nor the Official Notice teaches or suggests the specific structural arrangement and dual-mode functionality of the claimed ODP circuit, this aspect of the rejection should be withdrawn.”
This argument is partially found to be persuasive for the following reason. The amendment to the independent claims has eliminated the need for the previous official notice. Instead, the newly added secondary Nam reference reads upon the claimed limitations.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e. “deliver its output signal directly to a restoration circuit”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant argues for claims 3, 10, and 17:
“The Office Action contends that claims 3, 10, and 17 would have been obvious over Chen in view of Gunnam (U.S. 2021/0191733), which the Office Action relies upon for the feature of a first time period for receiving a first input signal at a first sub PE array overlapping a second time period for receiving a second input signal at a second sub PE array. Applicant respectfully disagrees. The claimed overlapping-reception feature does not merely describe pipelined or staggered data feeding within a single unified array; rather, it describes two structurally separate and independently operable sub PE arrays, each constituting its own systolic array in the second mode, simultaneously receiving different input signals at overlapping time periods. This enables the systolic array system to process entirely distinct computations in parallel across independent sub arrays, substantially reducing the total number of clock cycles required and increasing overall throughput. Gunnam's teaching of synchronized feeding of inputs and weights along clock cycles is directed to staggering the introduction of data to elements within a single unified systolic array to maintain regular, wave-front-style computation. In Gunnam, different elements receiving different data at the same clock cycle are all processing portions of the same matrix multiplication-not different independent computations. Critically, Chen's architecture, even when modified with Gunnam's pipelining approach, does not produce two independent sub PE arrays each receiving a different input signal at overlapping times; it merely introduces a staggered feeding schedule into an architecturally unchanged unified array. Neither Chen nor Gunnam recognizes the concept of sub PE arrays functioning as independent systolic arrays in a second mode, nor do they suggest enabling such sub arrays to concurrently receive different input signals. Accordingly, the combination of Chen and Gunnam fails to teach or suggest the claimed overlapping-reception feature, and this aspect of the rejection of claims 3, 10, and 17 should be withdrawn.”
This argument is not found to be persuasive for the following reason. Gunnam disclosed synchronizing the feeding of inputs and weights along clock cycles to a systolic array. A first input received by an array row/column (e.g. u12/2232/42 or u21-24) can be received while a second input is received by an array row/column (e.g. u11/21/31/41 or u11-14). This allows for the combination to read upon the overlapping first and second time periods.
Applicant argues regarding claims 4, 11, and 18:
“The Office Action rejects claims 4, 11, and 18 as obvious over Chen, Cho (U.S. 2022/0222315), and Narayanamoorthy (U.S. 2020/0265107), describing how Cho allegedly teaches preloading weight values and Narayanamoorthy teaches sparse dense matrix operations using a subset of processing elements. Applicant respectfully disagrees. The claims require that the plurality of sub PE arrays be preloaded with a condensed weight matrix in the second mode. As described in the Specification, a condensed weight matrix is specifically generated by a condensing circuit that divides the full weight matrix into sub-row matrices and deletes columns containing only zero values, thereby producing a structurally altered weight matrix with fewer columns. Each sub PE array is then preloaded with this condensed weight matrix so that it can independently perform a complete MAC computation processing only the non-zero columns, and the resulting partial output data must then be reconstructed by a restoration circuit using stored metadata. Narayanamoorthy achieves sparse processing by operating only a subset of processing elements while keeping the weight matrix architecturally intact; it does not teach removing zero-value columns from the weight matrix and preloading the resulting condensed matrix into each sub PE array so that each sub array independently completes a full MAC operation with fewer columns. This is a fundamentally different approach to sparsity: Narayanamoorthy reduces PE utilization; the claimed invention reduces the structural dimensions of the weight matrix and distributes the condensed matrix across independently operating sub arrays. Cho's teaching of preloading weight values for matrix and convolution operations is directed to preloading of a standard (uncondensed) weight matrix and provides no guidance toward generating or loading a dimensionally reduced, zero-column-free condensed weight matrix. Even combining all three references, the combination would yield a system that preloads some weights into some PEs, with some PEs deactivated for sparse inputs, categorically different from preloading a structurally condensed weight matrix into independently operating sub PE arrays with downstream output restoration. The rejection of claims 4, 11, and 18 should accordingly be withdrawn.”
This argument is not found to be persuasive for the following reason. Narayanamoorthy disclosed sparse-dense matrix processing. The combination allows for the sparse matrix to be the weight matrix, which is input into the array of Chen. Thus, reading upon the claimed limitations.
Applicant argues regarding the motivations to combine, number of references:
“The Office Action has not articulated any persuasive, evidence-based motivation for combining the cited references in the manner required to arrive at the claimed invention. For the rejection of claims 6-7, 13-14, and 20, the Office Action proposes adding generic multiplexers (via Official Notice) to Chen's L2 registers but provides no reason why one of ordinary skill in the art would configure those multiplexers to create a mode in which the ODP circuit output signal entirely exits the sub PE array hierarchy to reach a restoration circuit, a structural change that would require substantially rearchitecting Chen. For claims 3, 10, and 17, the Office Action combines Chen (which broadcasts inputs to a unified array) with Gunnam (which staggers inputs within a single unified array) and asserts that this results in overlapping reception at independent sub PE arrays; however, neither reference contemplates the creation of independently operable sub-array structures, and the proposed combination would not motivate one of ordinary skill in the art to restructure Chen into a system of parallel independent sub PE arrays. For claims 4, 11, and 18, the Office Action's three-reference combination requires: (a) generating a condensed weight matrix by column-removal (absent from all three references); (b) preloading that condensed matrix into each sub PE array (absent from all three references in combination); and (c) coupling the sub PE array outputs to a restoration circuit that uses metadata to reconstruct the output (absent from the combination). The absence of any individual reference, or plausible combination of references disclosing this integrated architecture confirms that the proposed combination is an analytical construct assembled after the fact, not a synthesis that one of ordinary skill in the art would have been independently motivated to pursue. The showing of obviousness is absent here, and the rejections should therefore be withdrawn.
Applicant respectfully submits that each of the foregoing rejections reflects impermissible hindsight. A telling indicator of hindsight is the Office Action's own analysis, in which the Office Action explicitly inverts the mode labels of Chen to match the Applicant's claim language (mapping "the second mode of Chen" to the "first mode" of the claims, and vice versa), demonstrating that the Office Action worked backward from the Applicant's disclosure to locate corresponding prior art support rather than assessing what one of ordinary skill in the art would have been motivated to combine independently. Similarly, the Office Action's resort to four separate references (Chen, Gunnam, Cho, and Narayanamoorthy), supplemented by Official Notice, to piece together limitations that are organically integrated in the claimed invention, is itself evidence that the claimed combination was not obvious to those in the art before the Applicant's contribution. No single reference teaches or suggests, and no subset of the references in combination teaches or suggests, the complete claimed architecture of independently operable sub PE arrays governed by ODP circuits having a mode-selectable sub output buffer and multiplexers, with weight preloading using a condensed weight matrix and downstream restoration. One of ordinary skill in the art reading these references without the benefit of the Applicant's disclosure would have had no reason to (a) restructure Chen's operational modes, (b) add ODP circuit multiplexers enabling a direct external output path in the second mode, (c) condense weight matrices by column removal rather than by deactivating PEs, or (d) enable independent parallel operation of sub PE arrays with metadata-driven output restoration. Applicant respectfully requests withdrawal of the rejections.”
This argument is not found to be persuasive for the following reason. The rejection includes proper reasons for combination, as outlined above.
In response to applicant's argument that the examiner has combined an excessive number of references, reliance on a large number of references in a rejection does not, without more, weigh against the obviousness of the claimed invention. See In re Gorman, 933 F.2d 982, 18 USPQ2d 1885 (Fed. Cir. 1991).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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