Prosecution Insights
Last updated: August 17, 2026
Application No. 19/014,672

DATA INITIALIZATION TECHNIQUES

Non-Final OA §101§103
Filed
Jan 09, 2025
Priority
Mar 15, 2019 — provisional 62/819,361 +4 more
Examiner
NAM, HYUN
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
763 granted / 881 resolved
+31.6% vs TC avg
Minimal -0% lift
Without
With
+-0.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
16 currently pending
Career history
896
Total Applications
across all art units

Statute-Specific Performance

§101
11.6%
-28.4% vs TC avg
§103
40.9%
+0.9% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 881 resolved cases

Office Action

§101 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 15, 17-18, and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The phrase, 'computer readable medium' in the claim 15 is a non-statutory subject matter (see MPEP 2106.01) because the disclosure defines the “medium” that does not exclude magnetic, optical, infrared, electromagnetic, and/or propagation medium and they can be construed to encompass an unpatentable wireless medium such as an electromagnetic carrier signal. Obvious-type Double Patenting (ODP) Rejections The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claims 1, 3-4, 6-8, 10-11, 13-15, 17-18 and 20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-4 of U.S. Patent 12,242,414) hereinafter ‘414. Although the conflicting claims are not identical, they are not patentably distinct from each other. For example, Claims ### of instant Application, respectively contain elements of claims ### of the *** ‘### as follows: Claims Instant Claims ‘414 1, 8, 15 processing circuitry memory metadata code map to cache line cache memory random number generator random numerical data metadata code indicates 1 processor circuitry cache memory metadata code map to cache line the cache memory random number generator random numerical data metadata code writing to 3, 10. 17 execute proximate entity consume random numerical data 2 (implicit) entity use random numerical data 4, 11, 18 writing metadata code generate a seed passed to the random number generator 3 1 (Implied) metadata code generate seed passed to random number generator 6, 13, 20 change the seed iterations 3 change iteration 7, 14, 20 graphic processing 4 graphic processing Therefore, claims 1-4 of the ‘414 anticipate(s) the instant application’s claims 1-20. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 4, 7, 8, 10, 11, 14, 15, 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Iyigun et al. (U.S. Publication 2010/0070701), hereinafter Iyigun in view of Chhabra et al. (U.S. Publication 2017/0185529), hereinafter Chhabra. Referring to claim 1, Iyigun teaches, as claimed, an apparatus comprising: processing circuitry (processor, see Fig. 8 and Paragraph 15) coupled to a memory (memory, see Fig. 8) the processing circuitry to: read one or more metadata codes (cache metadata, see Paragraph 62) which map (see Fig. 4) to one or more cache lines in a cache memory; and invoke a random number generator (random number generator, see Paragraph 62) to generate random numerical data (GUID or cache contents, see Paragraph 62) for the one or more cache in response to a determination that the one more metadata codes indicate (verified, see Paragraph 62) that the one or more cache are to contain the random numerical data (cache content, see Paragraph 62). Iyigun does not disclose expressly a cache line. Chhabra does disclose a cache line (see Abstract). At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Chhabra into Iyigun. The suggestion/motivation for doing so would have been to provide consistency of data writing. As to claim 2, the modification teaches the apparatus of claim 1, wherein the random number generator is positioned to execute proximate to an entity (user or machine, see Iyigun, Paragraph 85; Note, user is related to the processor) which is to consume the random numerical data. As to claim 4, the modification teaches the apparatus of claim 1, wherein the processing circuitry is further to: configure the cache memory by writing the one or more metadata codes which map to the one or more cache lines in the cache memory; and generate a seed (seeds, see Paragraph 35; Note, generating seed for RNG is commonly known practice) to be passed to the random number generator. As to claim 5, the modification teaches the apparatus of claim 1, wherein the random number generator is positioned to execute proximate to an entity (user or machine, see Iyigun, Paragraph 85; Note, user is related to the processor) which is to consume the random numerical data. As to claim 7, the modification teaches the apparatus of claim 1, wherein the processing circuitry comprises one or more of graphics processing circuitry or application processing circuitry (application programs, see Iyigun Paragraph 85). As to claims 8, 10, 11, 14, 17, 18, and 20, they are directed to a method/program to implement the device as set forth in claims 1, 3, 4, and 7. Therefore, they are rejected on the same basis as set forth hereinabove. Allowable Subject Matter Claims 6 and 13 would be allowable if rewritten or amended to overcome the rejection(s) under ODP, set forth in this Office action; and if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HYUN NAM/Primary Examiner, Art Unit 2183
Read full office action

Prosecution Timeline

Jan 09, 2025
Application Filed
Aug 03, 2026
Non-Final Rejection mailed — §101, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
86%
With Interview (-0.5%)
2y 6m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 881 resolved cases by this examiner. Grant probability derived from career allowance rate.

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