Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-9, 16-18, 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 4, 5, 7-14, 16-19 of app no: 18311733 . Claims 1, 8, 13-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 19, and 20 of app no: 16976368 . Although the claims at issue are not identical, they are not patentably distinct from each other because they are substantially similar in scope and they use the similar limitations to produce the same end result.
This is a nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. The instant application and the referenced copending application are claiming common subject matter, for illustration purposes only the method claims are shown below:
Instant Application
18311733
1. A method for operating a quantum read-only memory, the method comprising:
applying a data loading quantum circuit to qubits included in a control register, index register, and system register to perform an indexed operation and loading, conditioned on a state of one or more control qubits included in the control register, a data item corresponding to an index value l encoded in the index register to a l-th data qubit in the system register, wherein l represents an integer between zero and a maximum index value L, wherein the data loading quantum circuit comprises:
for each index value in a plurality of index values encoded by the index register that is less than the maximum index value in the plurality of index values, an implementation of the indexed operation that excludes a control on an index qubit representing 2bwhen i) a result of a bitwise-or operator applied to the index value and 2bis greater than or equal to the maximum index value and ii) a result of a bitwise-and operator applied to the maximum index value minus one and 2bis equal to 2b; and
one or more implementations of the indexed operation comprising respective controls on index qubits, wherein the respective controls on the index qubits comprise nested AND computations and uncomputations.
2. The method of claim 1, wherein the data loading quantum circuit further comprises: one or more sets of CNOT and NOT operations, wherein each set of CNOT and NOT operations implements an adjacent AND uncomputation and AND re-computation included in the nested AND computations and uncomputations with different control types.
4. The method of claim 1, wherein the data loading quantum circuit further comprises: one or more CNOT operations, wherein each CNOT operation implements an adjacent AND uncomputation and AND re-computation included in the nested AND computations and uncomputations with one pair of different control types.
2. A method performed by a quantum computing device that comprises:
quantum circuitry for implementing a unary iteration quantum circuit, the quantum circuitry comprising:
an index register comprising multiple index qubits;
a control register comprising multiple control qubits; and
a system register comprising multiple target qubits;
one or more control devices configured to operate the quantum circuitry; and
a classical processor in data communication with the quantum computing hardware, wherein the classical processor is configured to process and analyze measurement results obtained from the control devices;
wherein the method comprises:
applying the unary iteration quantum circuit to a plurality of qubits to perform a-single qubit unitary operation on an l-th target qubit in the register of target qubits, wherein l represents an integer between zero and a maximum index value L and performing the single qubit unitary operation is conditioned on a value encoded in an the index register comprising the multiple index qubits being equal to 1, wherein
the plurality of qubits comprises the multiple control qubits, the l-th target qubit, and the multiple index qubits;
the index register is configured to encode binary representations of a plurality of index values, the plurality of index values comprising integers between zero and the maximum index value L; and
the unary iteration quantum circuit comprises:
for each index value in the plurality of index values that is less than a-the maximum index value in the plurality of index values, an implementation of the single qubit unitary operation that excludes a control on an index qubit representing 2bwhen i) a result of a bitwise-or operator applied to the index value and 2bis greater than or equal to the maximum index value and ii) a result of a bitwise-and operator applied to the maximum index value minus one and 2bis equal to 2b';
one or more implementations of the single qubit unitary operation comprising respective controls on index qubits, wherein the respective controls on the index qubits comprise nested AND computations and uncomputations;
one or more sets of CNOT and NOT operations, wherein each set of CNOT and NOT operations implements an adjacent AND uncomputation and AND re- computation included in the nested AND computations and uncomputations with different control types; and
one or more CNOT operations, wherein each CNOT operation implements an adjacent AND uncomputation and AND re-computation included in the nested AND computations and uncomputations with one pair of different control types.
7. The method of claim 1, wherein the qubits further comprise one or more accumulator qubits and when a final control qubit is computed, a CNOT operation is performed between a corresponding accumulator qubit and a final control qubit, wherein the final control qubit acts as a control for the CNOT operation.
4. The method of claim 2, wherein the plurality of qubits comprises one or more accumulator qubits and when a final control qubit is computed, a CNOT operation between a corresponding accumulator qubit and a final control qubit, wherein the final control qubit acts as a control for the CNOT operation.
3. The method of claim 2, wherein the AND uncomputations and re-computations are nested so that lower controls are inside higher controls.
7. The method of claim 2, wherein the AND uncomputations and re- computations are nested so that lower controls are inside higher controls.
5. The method of claim 2, wherein a control qubit associated with an AND un-computation and re-computation is placed directly below its lowest input qubit
8. The method of claim 2, wherein a control qubit associated with an AND uncomputation and re-computation is placed directly below its lowest input qubit.
6. The method of claim 2, wherein a total number of AND uncomputations and re- computations included in the data loading quantum circuit is equal to the total number of target qubits N minus 1
9. The method of claim 2, wherein the total number of AND uncomputations and re-computations included in the unary iteration circuit is equal to the total number of target qubits N minus 1.
9. The method of claim 1, wherein performing the indexed operation has a T count of 4(L- 1), wherein L represents a number of data items in the quantum read-only memory
10. The method of claim 2, wherein performing the single qubit unitary operation has a T count of 4(L-1), wherein L represents an upper bound of values stored in the index register.
8. The method of claim 1, further comprising encoding the plurality of index values in the control qubits of the data loading quantum circuit, the encoding comprising, for each index value:
iteratively computing multiple logical AND operations between respective pairs of control qubits and index qubits to store a result of a logical AND operation between an inverse of a least significant index qubit and a penultimate control qubit storing a result of a previous logical AND operation in a final control qubit.
5. The method of claim 2, further comprising encoding the pluralityof index values in the control qubits of the unary iteration quantum circuit, the encoding comprising, for each index value:iteratively computing multiple logical AND operations between respective pairs of control qubits and index qubits to store a result of a logical AND operation between an inverse of a least significant index qubit and a penultimate control qubit storing a result of a previous logical AND operation in a final control qubit.
Instant Application
16976368
1. A method for operating a quantum read-only memory, the method comprising:
applying a data loading quantum circuit to qubits included in a control register, index register, and system register to perform an indexed operation and loading, conditioned on a state of one or more control qubits included in the control register, a data item corresponding to an index value l encoded in the index register to a l-th data qubit in the system register, wherein l represents an integer between zero and a maximum index value L, wherein the data loading quantum circuit comprises:
for each index value in a plurality of index values encoded by the index register that is less than the maximum index value in the plurality of index values, an implementation of the indexed operation that excludes a control on an index qubit representing 2bwhen i) a result of a bitwise-or operator applied to the index value and 2bis greater than or equal to the maximum index value and ii) a result of a bitwise-and operator applied to the maximum index value minus one and 2bis equal to 2b; and
one or more implementations of the indexed operation comprising respective controls on index qubits, wherein the respective controls on the index qubits comprise nested AND computations and uncomputations.
13. The method of claim 11, wherein the constructing further comprises applying a set of optimizations to the transformed circuit to generate the data loading quantum circuit, comprising, for each adjacent AND un-computation and AND re-computation:
removing the adjacent AND un-computation and AND re-computation when control types of the adjacent AND un-computation and AND re-computation match.
14. The method of claim 13, further comprising replacing the adjacent AND un-computation and AND re-computation with CNOT and NOT operations when no control types of the adjacent AND un-computation and AND re-computation match.
15. The method of claim 13, further comprising replacing the adjacent AND uncomputation and AND re-computation with CNOT operations when one pair of control types of the adjacent AND un-computation and AND re-computation match
1. A method for performing unary iteration to implement an indexed operation using a quantum computing device comprising a unary iteration quantum circuit, the method comprising: constructing the unary iteration circuit, comprising:defining a total-control circuit for implementing the indexed operation, the total- control circuit comprising a control register comprising multiple control qubits, one or more target qubits, and an index register comprising multiple index qubits, wherein the index register is configured to encode a plurality of index values;applying a set of transformations to the total-control circuit to generate a first transformed circuit, comprising, for each index value in the plurality of index values that is less than a maximum index value in the plurality of index values:removing a control of the indexed operation on an index qubit representing 2bwhen i) a result of a bitwise-or operator applied to the index value and 2bisgreater than or equal to the maximum index value and ii) a result of a bitwise-and operator applied to the maximum index value minus one and 2bis equal to2b; andexpanding remaining controls of the indexed operation into nested AND operations,applying a set of optimizations to the first transformed circuit to generate the unary iteration circuit, comprising, for each adjacent AND uncomputation and AND re- computation:removing the adjacent AND uncomputation and AND re-computation when control types of the adjacent AND uncomputation and AND re-computation match;replacing the adjacent AND uncomputation and AND re-computation with CNOT and NOT operations when no control types of the adjacent AND uncomputation and AND re-computation match, and
8. The method of claim 1, further comprising encoding the plurality of index values in the control qubits of the data loading quantum circuit, the encoding comprising, for each index value:
iteratively computing multiple logical AND operations between respective pairs of control qubits and index qubits to store a result of a logical AND operation between an inverse of a least significant index qubit and a penultimate control qubit storing a result of a previous logical AND operation in a final control qubit.
2. The method of claim 1, wherein encoding the index value in the control register of the unary iteration quantum circuit, the control register comprising multiple control qubits, comprises: iteratively computing multiple logical AND operations between respective pairs of control qubits and index qubits to store a result of a logical AND operation between an inverse of a least significant index qubit and a penultimate control qubit storing a result of a previous logical AND operation in a final control qubit.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claims recite a number of concepts which are indefinite which makes the inventive concept unclear
- It is recited that operations are conditioned on a bit value but does not specify how that works and furthermore presents an issue with optional recitation.
- Many elements regarding applying a quantum circuit,
- It is recited “for each index value” but is unclear what that is referring to especially when bit value in an index value is also recited
- The lack of specific details regarding the index value makes the claimed concept unclear
Dependent claims are rejected for depending off independent claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9, 11, 12, 16-18, 20 are/is rejected under 35 U.S.C. 103 as being unpatentable over Andrew M. Childs, Dmitri Maslov, Yunseong Nam, Neil J. Ross, Yuan Su, "Toward the first quantum simulation with quantum speedup" 11/29/2017,https://arxiv.org/pdf/1711.10980.pdf hereinafter referenced as Childs in view of Kuriyama et al. US2008/0104088
Regarding claim 1, Childs teaches: applying a data loading quantum circuit to qubits included in a control register, index register, and system register to perform an indexed operation and loading, conditioned on a state of one or more control qubits included in the control register, a data item corresponding to an index value l encoded in the index register to a l-th data qubit in the system register, wherein l represents an integer between zero and a maximum index value L, wherein the data loading quantum circuit comprises:
(Childs see section G.3 G.4 index and indices with particular values to be encoded and representing control register using a number of qubits such that registers can be controlled by a single qubit and implementing circuit uses target qubits, applying unitary operation conditioned on control register being in a particular state by cycling through a designated qubit using a reversible circuit)
for each index value in a plurality of index values encoded by the index register that is less than the maximum index value in the plurality of index values, an implementation of the indexed operation that excludes a control on an index qubit representing 2bwhen i) a result of a bitwise-or operator applied to the index value and 2bis greater than or equal to the maximum index value and ii) a result of a bitwise-and operator applied to the maximum index value minus one and 2bis equal to 2b; and (Childs see section G.4 cycle the value of ancilla qubit through Boolean products of w literals to be presented as cycling through 2w Boolean products to produce an optimized circuit)
one or more implementations of the indexed operation comprising respective controls on index qubits, wherein the respective controls on the index qubits comprise nested computations and uncomputations. (Childs see section D, G.4, uncomputes and computed operations of register for agreeing bits to be reversed in a reversible circuit consisting of NOT and CNOT gates.)
Childs does not distinctly disclose: AND operations
However, Kuriyama teaches: AND operations (Kuiryama see paragraph 0030 transformation including nested representation by performing AND operation)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include nesting AND operations as taught by Kuiryama for the predictable result of more efficiently processing data.
Regarding claim 2, Childs as modified further teaches: wherein the data loading quantum circuit further comprises: one or more sets of CNOT and NOT operations, wherein each set of CNOT and NOT operations implements an adjacent AND uncomputation and re-computation included in the nested computations and uncomputations with different control types. (Childs see section D, G.4, uncomputes and computed operations of register for agreeing bits to be reversed in a reversible circuit consisting of NOT and CNOT gates.)
Kuriyama teaches: AND operations (Kuiryama see paragraph 0030 transformation including nested representation by performing AND operation)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include nesting AND operations as taught by Kuiryama for the predictable result of more efficiently processing data.
Regarding claim 3, Childs as modified further teaches: wherein the AND uncomputations and re-computations are nested so that lower controls are inside higher controls. (Kuiryama see paragraph 0030 0043 0044 transformation including nested representation by performing AND operation and places all lower nodes of the second operation inside the node of the first operand of the highlighted operand)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include nesting AND operations as taught by Kuiryama for the predictable result of more efficiently processing data.
Regarding claim 4, Childs as modified further teaches: wherein the data loading quantum circuit further comprises: one or more CNOT operations, wherein each CNOT operation implements an adjacent uncomputation and re-computation included in the nested computations and uncomputations with one pair of different control types. (Childs see section D, G.4, uncomputes and computed operations of register for agreeing bits to be reversed in a reversible circuit consisting of NOT and CNOT gates.)
Kuriyama teaches: AND operations (Kuiryama see paragraph 0030 transformation including nested representation by performing AND operation)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include nesting AND operations as taught by Kuiryama for the predictable result of more efficiently processing data.
Regarding claim 5, Childs as modified further teaches: wherein a control qubit associated with an un-computation and re-computation is placed directly below its lowest input qubit. (Childs see section G.4 traversing the tree with a given depth represented as qubit such that vertices going up have not been explored and vertices below are already explored with the path starting and ending at the root)
Kuriyama teaches: AND operations (Kuiryama see paragraph 0030 transformation including nested representation by performing AND operation)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include nesting AND operations as taught by Kuiryama for the predictable result of more efficiently processing data.
Regarding claim 6, Childs as modified further teaches: wherein a total number of uncomputations and re- computations included in the data loading quantum circuit is equal to the total number of target qubits N minus 1. (Childs see section G.4 operations to reduce number of ancillas qubits to w-1)
Kuriyama teaches: AND operations (Kuiryama see paragraph 0030 transformation including nested representation by performing AND operation)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include nesting AND operations as taught by Kuiryama for the predictable result of more efficiently processing data.
Regarding claim 7, Childs as modified further teaches: wherein the qubits further comprise one or more accumulator qubits and when a final control qubit is computed, a CNOT operation is performed between a corresponding accumulator qubit and a final control qubit, wherein the final control qubit acts as a control for the CNOT operation. (Childs see section G.4 traversal of tree and repeating calculations to reduce gates including replacing Toffoli gates with CNOT gates)
Regarding claim 9, Childs as modified further teaches: wherein performing the indexed operation has a T count of 4(L- 1), wherein L represents a number of data items in the quantum read-only memory. (Childs see section G.4 page 47 figure shows circuiting show the operation performed using 4 T gates)
Regarding claim 11, Childs as modified further teaches: applying a set of transformations to a total-control circuit to generate a transformed circuit, comprising, for each index value in the plurality of index values that is less than the maximum index value: (Childs see sections G.2 G.4 circuit presented for select (v) operation based on implemented transformation using index values)
removing a control of the indexed operation on an index qubit representing 2bwhen i) a result of a bitwise-or operator applied to the index value and 2bis greater than or equal to the maximum index value and ii) a result of a bitwise-and operator applied to the maximum index value minus one and 2bis equal to 2b. (Childs see section G.4 cycle the value of ancilla qubit through Boolean products of w literals to be presented as cycling through 2w Boolean products to produce an optimized circuit)
Regarding claim 12, Childs as modified further teaches: wherein applying the set of transformations further comprises expanding remaining controls of the indexed operation into nested AND operations. (Kuiryama see paragraph 0030 transformation including nested representation by performing AND operation)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include nesting AND operations as taught by Kuiryama for the predictable result of more efficiently processing data.
Regarding claims 16-18, 20, note the rejection of claim(s) 1-7, 9, 11, 12. The instant claims recite substantially same limitations as the above-rejected claims and are therefore rejected under same prior-art teachings.
Claim(s) 8 are/is rejected under 35 U.S.C. 103 as being unpatentable over Andrew M. Childs, Dmitri Maslov, Yunseong Nam, Neil J. Ross, Yuan Su, "Toward the first quantum simulation with quantum speedup" 11/29/2017,https://arxiv.org/pdf/1711.10980.pdf hereinafter referenced as Childs in view of Kuriyama et al. US2008/0104088 in view of Macready et al. US2011/0231462
Regarding claim 8, Childs as modified teaches: further comprising encoding the plurality of index values in the control qubits of the data loading quantum circuit, the encoding comprising, for each index value:
iteratively computing multiple logical operations between respective pairs of control qubits and index qubits to store a result of a logical operation between an inverse of a least significant index qubit and (Childs see section C.2 G.3 G.4 equation for taylor series algorithm is repeated using values of qubits including negated or NOT values of qubits as Boolean products to cycle qubit through where each repetition or cycle is an iteration and negation reads on inverse)
Childs does not teach: logical AND operations, a penultimate control qubit storing a result of a previous logical AND operation in a final control qubit
However, Macready teaches: logical AND operations, a penultimate control qubit storing a result of a previous logical AND operation in a final control qubit. (Macready see paragraph 0030 0070 input qubits using AND gate resulting in output qubit)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include Boolean AND operators as taught by Macready for the predictable result of more efficiently processing data.
Claim(s) 10 are/is rejected under 35 U.S.C. 103 as being unpatentable over Andrew M. Childs, Dmitri Maslov, Yunseong Nam, Neil J. Ross, Yuan Su, "Toward the first quantum simulation with quantum speedup" 11/29/2017,https://arxiv.org/pdf/1711.10980.pdf hereinafter referenced as Childs in view of Kuriyama et al. US2008/0104088 in view of Massachusetts Institute of Technology, “Loading Classical Data into a Quantum Computer” 3/5/2018, https://arxiv.org/pdf/1803.01958 hereinafter referenced as MIT
Regarding claim 10, Childs as modified does not teach: wherein the state of the one or more control qubits specifies ON and OFF control types and wherein when the state is ON, the data item is loaded to the data register, and when the state is OFF, the data item is not loaded to the data register
However, MIT teaches: wherein the state of the one or more control qubits specifies ON and OFF control types and wherein when the state is ON, the data item is loaded to the data register, and when the state is OFF, the data item is not loaded to the data register. (MIT see section 2.4, controlled swap gates performing swapping of qubits on if control but is in a certain state otherwise it leaves the target unchanged where swap operation occur conditionally on control bits directly correspond to ON/OFF behavior)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include a method of swapping qubits as taught by MIT for the predictable result of more efficiently processing data.
Claim(s) 13 are/is rejected under 35 U.S.C. 103 as being unpatentable over Andrew M. Childs, Dmitri Maslov, Yunseong Nam, Neil J. Ross, Yuan Su, "Toward the first quantum simulation with quantum speedup" 11/29/2017,https://arxiv.org/pdf/1711.10980.pdf hereinafter referenced as Childs in view of Kuriyama et al. US2008/0104088 in view of Maslov, “Quantum Circuit Simplification and Level Compaction” 2/27/2008 https://arxiv.org/pdf/quant-ph/0604001
Regarding claim 13, Childs as modified further teaches: AND operation (Kuiryama see paragraph 0030 transformation including nested representation by performing AND operation)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include nesting AND operations as taught by Kuiryama for the predictable result of more efficiently processing data.
Childs as modified does not teach: optimizations to the transformed circuit to generate the data loading quantum circuit, comprising, for each adjacent un-computation and re-computation:
removing the adjacent un-computation and re-computation when control types of the adjacent un-computation and re-computation match
However, Maslov teaches: optimizations to the transformed circuit to generate the data loading quantum circuit, comprising, for each adjacent un-computation and re-computation:
removing the adjacent un-computation and re-computation when control types of the adjacent un-computation and re-computation match (Maslov see section 4.1, section 5, adjacent blocks being inverses then move them together and delete them, removing adjacent uncomputation and recomputation type when control types match is the gate inverse template once moving rules align the two inverse blocks)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include a method of moving and deleting adjacent blocks as taught by Maslov for the predictable result of more efficiently processing data.
Claim(s) 14 and 15 are/is rejected under 35 U.S.C. 103 as being unpatentable over Andrew M. Childs, Dmitri Maslov, Yunseong Nam, Neil J. Ross, Yuan Su, "Toward the first quantum simulation with quantum speedup" 11/29/2017,https://arxiv.org/pdf/1711.10980.pdf hereinafter referenced as Childs in view of Kuriyama et al. US2008/0104088 in view of Maslov, “Quantum Circuit Simplification and Level Compaction” 2/27/2008 https://arxiv.org/pdf/quant-ph/0604001 in view of University of Lethbridge, “Templates for Positive and Negative Control Toffoli Networks”, 12/16/2014, https://www.cs.uleth.ca/~rice/publications/ZamilurThesis.pdf
Regarding claim 14, Childs does not teach: further comprising replacing the adjacent AND un-computation and AND re-computation with CNOT and NOT operations when no control types of the adjacent AND un-computation and AND re-computation match.
However, Univeristy of Lethbridge teaches: further comprising replacing the adjacent AND un-computation and AND re-computation with CNOT and NOT operations when no control types of the adjacent AND un-computation and AND re-computation match. (Univeristy of Lethbridge see section 4.1.1, 4.1.4, 4.1.5, two adjacent CNOTs wit opposite polarities are replaced with a single NOT)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include a templates for Toffoli gates as taught by Univeristy of Lethbridge for the predictable result of more efficiently processing data.
Regarding claim 15, Childs does not teach: further comprising replacing the adjacent AND uncomputation and AND re-computation with CNOT operations when one pair of control types of the adjacent AND un-computation and AND re-computation match
However, Univeristy of Lethbridge teaches: further comprising replacing the adjacent AND uncomputation and AND re-computation with CNOT operations when one pair of control types of the adjacent AND un-computation and AND re-computation match. (Univeristy of Lethbridge see section 4.1.1, 4.1.4, 4.1.3, 4.1.5, pair reduces to a single gate with common controls, single gate becomes CNOT, with one pair of matching controls mixed polarity Toffoli templates collapse to just CNOTs)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified a quantum computing system as taught by Childs as modified to include a templates for Toffoli gates as taught by Univeristy of Lethbridge for the predictable result of more efficiently processing data.
Claim(s) 19 are/is rejected under 35 U.S.C. 103 as being unpatentable over Andrew M. Childs, Dmitri Maslov, Yunseong Nam, Neil J. Ross, Yuan Su, "Toward the first quantum simulation with quantum speedup" 11/29/2017,https://arxiv.org/pdf/1711.10980.pdf hereinafter referenced as Childs in view of Kuriyama et al. US2008/0104088 in view of University of Lethbridge, “Templates for Positive and Negative Control Toffoli Networks”, 12/16/2014, https://www.cs.uleth.ca/~rice/publications/ZamilurThesis.pdf
Regarding claim 19, see rejection of claim 15
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLEN S LIN whose telephone number is (571)270-0612. The examiner can normally be reached on M-F 9-5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kavita Stanley can be reached on (571)272-8352. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALLEN S LIN/Primary Examiner, Art Unit 2153