DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 6-14 in the reply filed on 07/20/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 2021/0397569), hereinafter referred to as Song in view of Chiu et al. (US 7,958,285), hereinafter referred to as Chiu.
Referring to claim 6, Song teaches, as claimed, an integrated circuit package, comprising: a first substrate including at least a first signal path and a second signal path (i.e.-a memory system on a substrate including channels CH1 and CH2, see fig. 2A/2B); a memory controller disposed in a first region of the first substrate (i.e.-memory controller 22a/22b, see fig. 2A/2b); an interface circuit disposed in a second region of the first substrate (i.e.-interface 32 disposed in memory package 30, see fig. 3), and electrically connected to the memory controller through the first signal path (i.e.-connected to memory controller 22a/b thru controller interface circuit, see figs. 3 and 2); and a memory apparatus disposed in a third region of the first substrate (i.e.-memory device 34_1/4 disposed in different region of the substrate of the memory system, see fig. 2A and fig. 3), and electrically connected to the memory controller through the second signal path (i.e.-connected to memory controller thru M-CH1/4, see fig. 3), and a frequency of signal transmitted between the memory controller and the interface circuit through the first signal path (page 5, ¶51, lines 2-6).
However, Song does not teach the frequency signal being greater than or equal to a frequency of signal transmitted between the interface circuit and the memory apparatus through the second signal path.
On the other hand, Chiu disclsoes a system and method to facilitate data transfers between independent clock domains on a chip, wherein a frequency signal of the high-speed bus being greater than or equal to a frequency of signal of the low-speed bus (col. 2, lines 37-43 and col. 3, lines 12-17 & 22-25).
Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Song so that the frequency signal being greater than or equal to a frequency of signal transmitted between the interface circuit and the memory apparatus through the second signal path, as taught by Chui. The motivation for doing so would have been to deterministically transfer data across different clock domains by altering the frequencies of the clock domains to be integer multiple of a single reference clock.
As to claim 7, the modified Song in view of Chiu teaches the integrated circuit package of claim 6, wherein the first signal path includes a first data bus electrically connecting the memory controller and the interface circuit (i.e.-C_CH1, see Song, page 6, ¶58, lines 6-8), and the second signal path includes a second data bus electrically connecting the interface circuit and the memory apparatus (i.e.-MCH1, see song, page 6, ¶58, lines 8-10), and wherein a number of data signals transmitted at one time through the first data bus is less than or equal to a number of data signals transmitted at one time through the second data bus (see Chiu, col. 2, lines 38-39).
As to claim 8, the modified Song teaches the integrated circuit package of claim 6, wherein the first substrate further includes a third signal path, and the third signal path is a direct access path between the memory controller and an external device (see Song, page 4, ¶41, lines 1-5 and page 6, ¶59, lines 12-14).
As to claim 9, the modified Song teaches the integrated circuit package of claim 6, wherein the first substrate further includes a fourth signal path, and the fourth signal path is a direct access path between the memory apparatus and an external device (see Song, page 4, ¶41, lines 1-5 and page 6, ¶58, lines 13-14).
As to claim 10, the modified Song innately teaches the integrated circuit package of claim 6, further comprising a second substrate disposed in the third region on the first substrate, wherein the memory apparatus is disposed on the second substrate, and the memory apparatus is electrically connected to the second signal path through the second substrate (see Song, page 7, ¶70).
As to claim 13, the modified Song teaches the integrated circuit package of claim 6, wherein the memory controller, the interface circuit, and the memory apparatus are each a separate chiplet (see Song, fig. 1).
Claim Objections
Claims 11, 12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tsai (US 9,076,506), Yoo et al. (US 6,898,659), Chen et al. (US 9,058,863), Ware et al. (US 8,824,224), Keckler et al. (US 9,058,453), Ali et al. (US 12,450,178) and Ilda et al. (US 2008/0276032) do teach method and system for interfacing memory device and memory controller thru plurality of communication channels to facilitate data transfer between independent clock domains.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM.
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/Elias Mamo/Primary Examiner, Art Unit 2184
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