Prosecution Insights
Last updated: July 17, 2026
Application No. 19/014,996

Modular, Multicell, and Multilevel Inverter

Non-Final OA §102
Filed
Jan 09, 2025
Priority
Jan 09, 2024 — provisional 63/619,229
Examiner
NASH, GARY A
Art Unit
Tech Center
Assignee
Board of Regents of the University of Texas System
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
478 granted / 538 resolved
+28.8% vs TC avg
Minimal +5% lift
Without
With
+4.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
11 currently pending
Career history
543
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
63.9%
+23.9% vs TC avg
§102
30.0%
-10.0% vs TC avg
§112
2.9%
-37.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 538 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 2. This action is in response to application filed on January 9, 2025. Information Disclosure Statement 3. The information disclosure statement (IDS) submitted on 4/10/2025 has been considered by the examiner. Drawings 4. The drawings were received on January 9, 2025. These drawings are accepted. Claim Rejections - 35 USC § 102 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 6. Claims 1-5 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zargari et al (US 2018/0145578). Regarding claim 1, Zargari et al discloses a modular, multicell, multi-level power conversion system (i.e. circuit of Figure 1) comprising: a set of cascading H-bridge cells (Fig. 1, power cells 100-U1 – 100-U6), including a first H-bridge cell (Fig. 1, power cell 100-U1) and a second H-bridge cell (Fig. 1, power cell 100-U2), each of the first (Fig. 1, power cell 100-U1) and second H-bridge cell (Fig. 1, power cell 100-U2) as a modular unit cell (Fig. 3, power cell 100) (note that Figure 3 is related to Figure 1 since Figure 3 discloses the power cells as seen in Figure 1) including: four switches (Fig. 3, switches Q1-Q4) arranged in a H-bridge configuration (Fig. 3, configuration of switches Q1-Q4); terminals (Fig. 3, DC link terminals 131-132) to a DC power source (Fig. 3, DC link circuit 130), the terminals (Fig. 3, DC link terminals 131-132) located parallel to the H-bridge configuration (Fig. 3, configuration of switches Q1-Q4); and a fifth switch (Fig. 3, bypass switches 102 or 103A-B) connecting the modular unit cell (Fig. 3, power cell 100) to a next unit cell (Fig. 1, power cells 100-U1 – 100-U6) in the set of cascading H-bridge cells (Fig. 1, power cells 100-U1 – 100-U6) (i.e. cascaded H-bridge power stages 100U-1 – 100U-6 have outputs 104U-1 – 104U-6 connected in series with one another. See ¶[0024]), wherein the fifth switch (Fig. 3, bypass switches 102 or 103A-B), along with the respective four switches (Fig. 3, switches Q1-Q4) of the modular unit cell (Fig. 3, power cell 100) and the next modular unit cell (Fig. 3, power cell 100), are configured to collectively form a new H-bridge between them that links together the respective terminals to the DC power sources (Fig. 3, DC link circuit 130) of the modular unit cell (Fig. 3, power cell 100) and the next modular unit cell (Fig. 3, power cell 100) in a parallel connection. Regarding claim 2, Zargari et al further discloses wherein the fifth switch (Fig. 3, bypass switch 103A) is connected in series along a positive bus (Fig. 3, connection along first internal node 141 with switch 103A) located between the first H-bridge cell (Fig. 1, power cell 100-U1) and the second H-bridge cell (Fig. 1, power cell 100-U2). Regarding claim 3, Zargari et al further discloses wherein the fifth switch (Fig. 3, bypass switches 102 or 103A-B) includes at least one of: (i) two MOSFETs (i.e. multiple electrical switching devices. See ¶[0031]) or (ii) two IGBTs, arranged to block current flow in a first direction from the modular unit cell (Fig. 3, power cell 100) to the next modular unit (Fig. 3, power cell 100) and a second direction from the next modular unit cell (Fig. 3, power cell 100) to the modular unit (Fig. 3, power cell 100) (See ¶[0031]). Regarding claim 4, Zargari et al further discloses wherein the fifth switch (Fig. 3, bypass switch 103B) is connected in series along a negative bus (Fig. 3, connection along second internal node 142 with switch 103B) located between the first H-bridge cell (Fig. 1, power cell 100-U1) and the second H-bridge cell (Fig. 1, power cell 100-U2). Regarding claim 5, Zargari et al further discloses wherein the fifth switch (Fig. 3, bypass switch 102) is connected in parallel between the first H-bridge cell (Fig. 1, power cell 100-U1) and second H-bridge cell (Fig. 1, power cell 100-U2). Regarding claim 9, Zargari et al discloses a modular, multicell, multi-level power conversion system (i.e. circuit of Figure 1) comprising: a set of cascading half-bridge cells (Fig. 1, power cells 100-U1 – 100-U6), including a first half-bridge cell (Fig. 1, power cell 100-U1) and a second half- bridge cell (Fig. 1, power cell 100-U2), each of the first (Fig. 1, power cell 100-U1) and second half-bridge cell (Fig. 1, power cell 100-U2) as a modular unit cell (Fig. 3, power cell 100) (note that Figure 3 is related to Figure 1 since Figure 3 discloses the power cells as seen in Figure 1) including: two switches (Fig. 3, switches Q1-Q2 or switches Q3-Q4) arranged in a half-bridge configuration (Fig. 3, configuration of switches Q1-Q2 or switches Q3-Q4); terminals (Fig. 3, DC link terminals 131-132) to a DC power source (Fig. 3, DC link circuit 130), the terminals (Fig. 3, DC link terminals 131-132) located parallel to the half-bridge configuration (Fig. 3, configuration of switches Q1-Q4); and a third switch (Fig. 3, bypass switches 102 or 103A-B) that connects the modular unit cell (Fig. 3, power cell 100) to a next modular unit cell (Fig. 1, power cells 100-U1 – 100-U6) in the set of cascading half-bridge cells (Fig. 1, power cells 100-U1 – 100-U6) (i.e. cascaded H-bridge power stages 100U-1 – 100U-6 have outputs 104U-1 – 104U-6 connected in series with one another. See ¶[0024]), wherein the third switch (Fig. 3, bypass switches 102 or 103A-B) and the respective two switches (Fig. 3, switches Q1-Q2 or switches Q3-Q4) of the modular unit cell (Fig. 3, power cell 100) and the next modular unit cell (Fig. 1, power cells 100-U1 – 100-U6) are configured to operate to collectively form a new half-bridge between the modular unit cell (Fig. 3, power cell 100) and the next modular unit cell (Fig. 1, power cells 100-U1 – 100-U6) that links together the respective terminals to the DC power sources (Fig. 3, DC link circuit 130) of the modular unit cell (Fig. 3, power cell 100) and the next modular unit cell (Fig. 1, power cells 100-U1 – 100-U6) in parallel connection. Allowable Subject Matter 7. Claims 15-19 are allowed. 8. Claims 6-8 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 9. The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 6-8, the prior art fails to disclose or suggest the emboldened and italicized features below: A modular, multicell, multi-level power conversion system, wherein the system is configured as an N-cell CHB or N-cell MMC, the system comprising N-1 number of the fifth switches. Regarding claims 10-11, the prior art fails to disclose or suggest the emboldened and italicized features below: A modular, multicell, multi-level power conversion system, wherein the terminals to the DC power source of the first half bridge cell are configured to couple to a DC source, and wherein the terminals to the DC power source of the second half bridge cell and the other half bridge cells are configured to couple to a DC capacitor, and the circuit is configured to form a charge pump DC/DC converter. Regarding claims 12-14, the prior art fails to disclose or suggest the emboldened and italicized features below: A modular, multicell, multi-level power conversion system, wherein the terminals to the DC power source of the first half-bridge cell are configured to couple to a DC source, and wherein the terminals to the DC power source of the second half-bridge cell and the other half-bridge cells are configured to couple to a DC capacitor, and the circuit is configured to form a bi-directional charge pump DC/DC converter, wherein a switch and a capacitor is connected to the output of the last half bridge cell. Regarding claims 15-19, the prior art fails to disclose or suggest the emboldened and italicized features below: A modular, multicell, multi-level power conversion system comprising: a set of cascading H-bridge cells, including a first H-bridge cell and a second H-bridge cell, each of the first and second H-bridge cell as a modular unit cell including: four switches arranged in a H-bridge configuration; terminals to a DC power source, the terminals located parallel to the H-bridge configuration; and a fifth switch connecting the modular unit cell to a next unit cell in the set of cascading H-bridge cells, wherein the fifth switch, along with the respective four switches of the modular unit cell and the next modular unit cell, are configured to collectively form a new H-bridge between them that links together the respective terminals to the DC power sources of the modular unit cell and the next modular unit cell in a parallel connection; a first set of cascading H-bridge cells, including the first and second H-bridge cells, wherein the DC terminals of the first set of cascading H-bridge cells are connected to a respective capacitor bank; a second set of cascading H-bridge cells, including a third H-bridge cell and a fourth H- bridge cell, where the DC terminals of the second set of cascading H-bridge cells are connected to a respective capacitor bank; and an additional H-bridge cell that is coupled to a DC voltage source, wherein the first set of cascading H-bridge cells, the second set of cascading H-bridge cells, and the additional H-bridge cell collectively form an inverter. Conclusion 10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lai et al (US 2022/0247326) deals with a hybrid multi-level inverter, Rivera Abarca et al (US 2022/0224245) deals with a multilevel power converter circuit, Vavilpalli et al (US 2021/0211066) deals with a buck-chopper and bi-directional chopper for multilevel cascaded hbridge inverters, and Zhao et al (US 2018/0091037) deals with a four-port power electronic transformer based on hybrid modular multilevel converter. 11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY NASH whose telephone number is (571) 270-3349. The examiner can normally be reached on Monday-Friday 8am-4pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner‘s supervisor, Thienvu Tran can be reached on (571) 270-1276. The fax number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GARY A NASH/Primary Examiner, Art Unit 2838
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Prosecution Timeline

Jan 09, 2025
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
94%
With Interview (+4.8%)
2y 2m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 538 resolved cases by this examiner. Grant probability derived from career allowance rate.

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