DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to amendment filed on 7/10/2026.
Claim 10 has been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Medeiros et al. (US 2025/0307189).
With respect to claim 10, Medeiros teaches of a memory sub-system, comprising: a memory space accessible to a host system using a memory access protocol (fig. 1, 7; paragraph 51-56; where the host device accesses data in the cache memory when a cache slot has already been allocated for the LBA and retrieves the data from the cache slot and returns it to the host device. These steps outline the protocol for accessing the cache slot);
a storage space accessible to the host system using a storage access protocol (fig. 1, 7; paragraph 51-56; where the host device accesses data in the storage medium by a DMA write from the storage medium to the cache slot and then by retrieving the data form the cache slot and returning it to the host. These steps outline the protocol for accessing the storage medium); and
a controller configured to: execute a storage access request to retrieve, from at least a logical block address in the storage space, data according the logical block address provided in the storage access request (fig. 7; paragraph 51-56; where a read request results in the return of the data at the provided LBA).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros et al. (US 2025/0307189) and Gorrle et al. (US 2024/0086071).
With respect to claim 1, Medeiros teaches of a method, comprising: communicating, from a host system to a memory sub-system, a storage access request identifying a logical block address in a storage space of the memory sub-system (fig. 1, 7; paragraph 51; where the storage processor receives a read request including an LBA from a host device);
allocating, by the memory sub-system, the block of memory from the memory space of the memory sub-system (fig. 7; paragraph 54; where the storage processor allocates a cache slot to the LBA associated with the read request); and
loading, from the storage space according to the logical block address and to the block of memory, data during execution of the storage access request (fig. 7; paragraph 55; where the data associated with the LBA is stored into the allocated cache slot).
Medeiros fails to explicitly teach of determining, based on the storage access request, a size of a block of memory to be allocated from a memory space of the memory sub-system.
However, Gorrle teaches of a storage access request identifying a logical block address in a storage space of the memory sub-system (paragraph 62; where the read command from the host includes the LBA and a data length);
determining, based on the storage access request, a size of a block of memory to be allocated from a memory space of the memory sub-system (paragraph 62; where the read command from the host includes the LBA and a data length. In the combination with Medeiros, as a cache slot is allocated for the data (Medeiros paragraph 54), the size allocated accommodates the length of the data).
Medeiros and Gorrle are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros and Gorrle before the time of the effective filing of the claimed invention to include the command fields including the data length of Gorrle’s read data in read commands in the read commands of Medeiros. Their motivation would have been to ensure space is available to store the read data.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros and Gorrle as applied to claim 1 above, and further in view of Miller et al. (US 2020/0004686).
With respect to claim 2, Medeiros teaches of loading, in response to the host system executing one or more load instructions, a portion of the data from the block of memory to the host system using a memory access protocol over a connection between the host system and the memory sub-system (fig. 7; paragraph 56; where the data is retrieved from the cache slot and returned to the sender of the read request. As the data is read out from the cache slot and sent back to the host, it must have occurred via memory access protocol via a connection).
The combination of Medeiros and Gorrle fails to explicitly teach of communicating, from the memory sub-system to the host system, a starting memory address of the block of memory via a completion record generated for the storage access request.
However, Miller teaches of communicating, from the memory sub-system to the host system, a starting memory address of the block of memory via a completion record generated for the storage access request (paragraph 38; where the tag data and the cache line are returned).
Medeiros, Gorrle, and Miller are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros, Gorrle, and Miller before the time of the effective filing of the claimed invention to include the cached tag address with the returned data in the combination of Medeiros and Gorrle as taught in Miller. Their motivation would have been to more efficiently access the memory (Miller paragraph 14-15).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros, Gorrle, and Miller as applied to claim 2 above, and further in view of Chachad et al. (US 2020/0371934).
With respect to claim 5, the combination of Medeiros, Gorrle, and Miller fails to explicitly teach of wherein the storage access request includes an opcode configured to cause the memory sub-system to allocate the block of memory during execution of the storage access request.
However, Chachad teaches of wherein the storage access request includes an opcode configured to cause the memory sub-system to allocate the block of memory during execution of the storage access request (fig. 11-12; paragraph 120, 124; where the opcodes of coherent and non-coherent allocating read requests are mapped by the opcode mapping logic to read exclusive and read command without snoop opcodes).
Medeiros, Gorrle, Miller, and Chachad are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros, Gorrle, Miller, and Chachad before the time of the effective filing of the claimed invention to include the opcodes and opcode mapping logic of Chachad in the combination of Medeiros, Gorrle, and Miller. Their motivation would have been to more efficiently maintain coherency in the cache memory.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros, Gorrle, and Miller as applied to claim 2 above, and further in view of Nimmagadda et al. (US 2020/0225874).
With respect to claim 6, the combination of Medeiros, Gorrle, and Miller fails to explicitly teach of wherein the storage access request includes a scatter gather list (SGL) configured to cause the memory sub-system to allocate the block of memory during execution of the storage access request.
However, Nimmagadda teaches of wherein the storage access request includes a scatter gather list (SGL) configured to cause the memory sub-system to allocate the block of memory during execution of the storage access request (paragraph 9; where in response to the read command, a read buffer is allocated in the read/write data buffer and maps one or more scattered gathered list (SGL) address(es) from the read command to the allocated read buffer address).
Medeiros, Gorrle, Miller and Nimmagadda are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros, Gorrle, Miller and Nimmagadda before the time of the effective filing of the claimed invention to include the SGL in the commands of the combination of Medeiros and Gorrle as taught in Nimmagadda. Their motivation would have been to more efficiently access the locations corresponding to the commands.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros, Gorrle, Miller and Nimmagadda as applied to claim 6 above, and further in view of Morrison et al. (US 2012/0254562).
With respect to claim 7, the combination of Medeiros, Gorrle, Miller and Nimmagadda fails to explicitly teach of wherein the storage access request includes an opcode configured to cause the memory sub-system to at least read the data from the storage space.
However, Morrison teaches of wherein the storage access request includes an opcode configured to cause the memory sub-system to at least read the data from the storage space (fig. 5; paragraph 41; where the command contains a read modify write command opcode, which reads the data, modifies it, and writes the data back to the LBA).
Medeiros, Gorrle, Miller, Nimmagadda, and Morrison are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros, Gorrle, Miller, Nimmagadda, and Morrison before the time of the effective filing of the claimed invention to include the RMW commands of Morrison in the commands of the combination of Medeiros, Gorrle, Miller and Nimmagadda. Their motivation would have been to more efficiently carry out operations on the storage.
With respect to claim 8, Morrison teaches of wherein the opcode is further configured to cause the memory sub-system to write data to the storage space according to the logical block address (fig. 5; paragraph 41; where the command contains a read modify write command opcode, which reads the data, modifies it, and writes the data back to the LBA).
The reasons for obviousness are the same as indicated above with respect to claim 7.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros, Gorrle, and Miller as applied to claim 2 above, and further in view of Rao et al. (US 20190377516).
With respect to claim 9, the combination of Medeiros, Gorrle, and Miller fails to explicitly teach of wherein the communicating of the storage access request is via a submission queue configured for the memory sub-system according to a storage access protocol; and the communicating of the starting memory address is via a completion queue configured for the memory sub-system.
However, Rao teaches of wherein the communicating of the storage access request is via a submission queue configured for the memory sub-system according to a storage access protocol; and the communicating of the starting memory address is via a completion queue configured for the memory sub-system (fig. 2-3; paragraph 42, 45-46; where the host device, storage manager, and storage devices each contain their own submission queue and completion queues that correspond to each other. In the combination with Medeiros, the read request from the host is transmitted over the submission queue to the storage manager from the host and the completion message including the cache tag of Miller is send using the completion queue to the host).
Medeiros, Gorrle, Miller, and Rao are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros, Gorrle, Miller, and Rao before the time of the effective filing of the claimed invention to include the completion and submission queues of Rao into the combination of Medeiros, Gorrle, and Miller. Their motivation would have been to more efficiently communicate between the host and storage.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros and Miller.
With respect to claim 11, Medeiros teaches of wherein the controller is further configured to: allocate, in response to the storage access request, a block of memory from the memory space (fig. 7; paragraph 54; where the storage processor allocates a cache slot to the LBA associated with the read request);
store at least a portion of the data in the block of memory (fig. 7; paragraph 55; where the data associated with the LBA is stored into the allocated cache slot);
control, based at least in part on allocation of the block of memory during execution of the storage access request, access from outside of the memory sub-system to the block of memory (fig. 7; paragraph 51-56; where a read request by a host device which is outside the storage array results in the return of the data at the provided LBA to the host device via the allocated cache slots).
Medeiros fails to explicitly teach of provide, in a completion record for the storage access request, a starting memory address of the block of memory.
However, Miller teaches of provide, in a completion record for the storage access request, a starting memory address of the block of memory (paragraph 38; where the tag data and the cache line are returned).
Medeiros and Miller are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros and Miller before the time of the effective filing of the claimed invention to include the cached tag address with the returned data in Medeiros as taught in Miller. Their motivation would have been to more efficiently access the memory (Miller paragraph 14-15).
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros and Miller as applied to claim 11 above and in further view of Hatakeyama (US 2008/0282093).
With respect to claim 12, the combination of Medeiros and Miller fails to explicitly teach wherein the controller is further configured to: determine an identification of a processor associated with the storage access request to allow the processor to access from outside of the memory sub-system to the block of memory.
However, Hatakeyama teaches of wherein the controller is further configured to: determine an identification of a processor associated with the storage access request to allow the processor to access from outside of the memory sub-system to the block of memory (paragraph 56, 72, 88; where the controller determines the processor ID from the command to determine if the processor has authority to access the memory. As shown in fig. 2; the processor is external from the trusted storage region and in the combination with Medeiros, the host device is connected via the network to the storage array, see fig. 1).
Medeiros, Miller, and Hatakeyama are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros, Miller, and Hatakeyama before the time of the effective filing of the claimed invention to include the trusted data storage and the processor ID authentication of Hatakeyama in the combination of Medeiros and Miller. Their motivation would have been to ensure only better security for accessing the data (Hatakeyama paragraph 3-4).
With respect to claim 13, Hatakeyama teaches of wherein the storage access request is configured to include the identification of the processor (paragraph 56, 72, 88; where the command includes the processor ID).
The reasoning for obviousness is the same as indicated above with respect to claim 12.
With respect to claim 14, Hatakeyama teaches of wherein the identification of the processor is determined from a memory access request directed to a memory address in the block of memory and received in the memory sub-system after the completion record is provided with the starting memory address of the block of memory (paragraph 56, 72, 88; where in the combination, the commands all include the processor ID to ensure appropriate access is granted. This includes the commands after the return of the read data and corresponding cache tag).
The reasoning for obviousness is the same as indicated above with respect to claim 12.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros, Miller, and Hatakeyama as applied to claim 12 above and in further view of Rao.
With respect to claim 15, the combination of Medeiros, Miller, and Hatakeyama fails to explicitly teach of wherein the storage access request is retrieved from a submission queue configured in the memory space; and the identification of the processor is determined based on a memory access request to store the storage access request to the submission queue.
However, Rao teaches of wherein the storage access request is retrieved from a submission queue configured in the memory space (fig. 2-3; paragraph 42, 45-46; where the host device, storage manager, and storage devices each contain their own submission queue and completion queues that correspond to each other. In the combination with Medeiros, the read request from the host is transmitted over the submission queue to the storage manager from the host).
The combination of Medeiros, Miller, Hatakeyama, and Rao teaches of the identification of the processor is determined based on a memory access request to store the storage access request to the submission queue (Rao, paragraph 42, 45-46; Hatakeyama, paragraph 56, 72, 88 In the combination the a write request with the processor ID of Hatakeyama is stored into the submission queue of Rao as the operation is being transmitted from the host device to the storage).
Medeiros, Miller, Hatakeyama and Rao are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros, Miller, Hatakeyama and Rao before the time of the effective filing of the claimed invention to include the completion and submission queues of Rao into the combination of Medeiros, Miller, Hatakeyama. Their motivation would have been to more efficiently communicate between the host and storage.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros and Rao.
With respect to claim 16, Medeiros teaches of a non-transitory computer storage medium storing instructions which, when executed in a computing system, cause the computing system to perform a method (paragraph 5, 63; where program code is stored in memory and executed on a processor to perform the disclosed operations), comprising:
configuring, in a storage access request, a logical block address in a storage space of a memory sub-system and a memory request (fig. 1, 7; paragraph 50-51; where the storage processor receives a read request and LBA from one of the host devices for data in the memory); and
entering the storage access request to cause the memory sub-system to allocate a block of memory from a memory space of the memory sub-system during execution of the storage access request (fig. 7; paragraph 51, 54; where the storage processor allocates a cache slot to the LBA associated with the received read request).
Medeiros fail to explicitly teach of entering the storage access request in a submission queue configured for the memory sub-system to cause the memory sub-system to allocate a block of memory from a memory space of the memory sub-system during execution of the storage access request.
However, Rao teaches of entering the storage access request in a submission queue configured for the memory sub-system (fig. 2-3; paragraph 42, 45-46; where the host device, storage manager, and storage devices each contain their own submission queue and completion queues that correspond to each other. In the combination with Medeiros, the read request from the host is transmitted over the submission queue to the storage manager from the host).
The combination of Medeiros and Rao teaches of entering the storage access request in a submission queue configured for the memory sub-system to cause the memory sub-system to allocate a block of memory from a memory space of the memory sub-system during execution of the storage access request (Medeiros, fig. 7; paragraph 51, 54; Rao, fig. 2-3; paragraph 42, 45-46; where the host device, storage manager, and storage devices each contain their own submission queue and completion queues that correspond to each other. In the combination with Medeiros, the read request from the host is transmitted over the submission queue to the storage manager from the host).
Medeiros and Rao are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros and Rao before the time of the effective filing of the claimed invention to include the completion and submission queues of Rao into Medeiros. Their motivation would have been to more efficiently communicate between the host and storage.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Medeiros and Rao as applied to claim 16 above and in further view of Miller.
With respect to claim 17, Rao teaches of wherein the accessing of the block of memory includes: executing one or more load instructions to load, from the block of memory, data retrieved from the storage space via execution of the storage access request (fig. 2-3; paragraph 42, 45-46; where the host device, storage manager, and storage devices each contain their own submission queue and completion queues that correspond to each other for transmission between them. As requests are added and removed from the queues, this suggests to one of ordinary skill in the art that a load instruction is used to read requests from the queues).
The combination of Medeiros and Rao fails to explicitly teach of extracting, from a completion record retrieved from a completion queue for the storage access request, a starting memory address of the block of memory; and accessing, based on the starting memory address, the block of memory in the memory sub-system.
However, Miller teaches of communicating, from the memory sub-system to the host system, a starting memory address of the block of memory via a completion record generated for the storage access request (paragraph 38; where the tag data and the cache line are returned).
The combination of Medeiros, Rao, and Miller teaches of extracting, from a completion record retrieved from a completion queue for the storage access request, a starting memory address of the block of memory; and accessing, based on the starting memory address, the block of memory in the memory sub-system (Medeiros, fig. 1; paragraph 50-52, 55-56; Rao, fig. 2-3; paragraph 42, 45-46; Miller, paragraph 38; where in the combination, the returned address is used in a read request to access the data and as it is already in the cache, a new slot isn’t allocated and the data is returned to the host).
Medeiros, Rao, and Miller are analogous art because they are from the same field of endeavor, as they are directed to data access.
It would have been obvious to one of ordinary skill in the art having the teachings of Medeiros, Rao, and Miller before the time of the effective filing of the claimed invention to include the cached tag address with the returned data in the combination of Medeiros and Rao as taught in Miller. Their motivation would have been to more efficiently access the memory (Miller paragraph 14-15).
With respect to claim 18, Rao teaches of wherein the submission queue is configured in the memory space of the memory sub-system; and the method further comprises: executing one or more store instructions to store the storage access request in the submission queue in the memory space of the memory sub-system (fig. 2-3; paragraph 42, 45-46; where the host device, storage manager, and storage devices each contain their own submission queue and completion queues that correspond to each other for transmission between them. As requests are added and removed from the queues, this suggests to one of ordinary skill in the art that a store instruction is used to add requests to the queues).
The reasons for obviousness are the same as indicated above with respect to claim 16.
With respect to claim 19, Rao teaches of wherein the completion queue is configured in a memory of the host system (fig. 2-3; paragraph 42, 45-46; where the host device, storage manager, and storage devices each contain their own submission queue and completion queues that correspond to each other for transmission between them).
The reasons for obviousness are the same as indicated above with respect to claim 16.
Allowable Subject Matter
Claims 3-4 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 3-4 and 20, Nakagawa et al. (US 2009/0228670) discloses a volume management table where if a volume is not allocated to the host computer, "null" is stored in the allocation destination field to show that a volume can be allocated in figure 6 and paragraph 47.
The prior art does not teach or suggest, “wherein the storage access request is configured with a null memory address to cause the memory sub-system to allocate the block of memory during execution of the storage access request,” in the context of the claims.
Response to Arguments
Applicant's arguments filed 7/10/2026 have been fully considered but they are not persuasive.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “techniques to facilitate efficient access of a storage space of a memory sub-system at a granularity level smaller than the level of an atomic read or write operation in the memory sub-system in retrieving data from memory cells or programming data into the memory cells”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant appears to argue regarding claim 1, that the combination of Medeiros and Gorrle does not teach of determining, based on the storage access request, a size of a block of memory to be allocated from a memory space of the memory sub-system; allocating, by the memory sub-system, the block of memory from the memory space of the memory sub-system; and loading, from the storage space according to the logical block address and to the block of memory, data during execution of the storage access request. The examiner disagrees.
Gorrle discloses a storage access request identifying a logical block address in a storage space of the memory sub-system in paragraph 62 where the read command from the host includes the LBA and a data length. This disclosed data length received with the read command also reads on the claimed determining, based on the storage access request, a size of a block of memory to be allocated from a memory space of the memory sub-system; where the read command from the host includes the data length of the read, thus the size of memory to be allocated has been determined.
Medeiros discloses allocating, by the memory sub-system, the block of memory from the memory space of the memory sub-system in figure 7 and paragraph 54, where the storage processor allocates a cache slot to the LBA associated with the read request. Medeiros goes on to detail how the data associated with the LBA is read and stored into the allocated cache slot in figure 7 and paragraph 55, thus reading on the claimed, “loading, from the storage space according to the logical block address and to the block of memory, data during execution of the storage access request.”
Thus, the combination of Medeiros and Gorrle reads on the invention of claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Huo (US 2022/0308993) discloses host side mapping managing of a memory subsystem.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138
