DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, and 3-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11676322 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations in claim 1 is anticipated by claim 1 and claim 9 of the U.S. Patent No. US 11676322 B2.
Application 19015406
Claim 1
US 11676322 B2
Claim 1
1. A graphics processor comprising:
1. A graphics processor comprising:
a block of graphics cores; and
a block of graphics cores; and
circuitry including a programmable neural network unit,
circuitry including a programmable neural network unit,
the programmable neural network unit including one or more neural network hardware blocks,
the programmable neural network unit including one or more neural network hardware blocks,
wherein a neural network hardware block includes circuitry to perform neural network operations and activation operations for a layer of a neural network,
wherein a neural network hardware block includes circuitry to perform neural network operations and activation operations for a layer of a neural network,
the programmable neural network unit addressable by cores within the block of graphics cores,
the programmable neural network unit addressable by cores within the block of graphics cores,
wherein the programmable neural network unit is to configure one or more neural network hardware blocks with a meta-shader neural network, the meta-shader neural network to generate a texture for one of multiple types of terrain.
9. The graphics processor as in claim 1, wherein the programmable neural network unit is to configure one or more neural network hardware blocks with a meta-shader neural network, the meta-shader neural network to generate a texture for one of multiple indicated types of terrain.
the programmable neural network unit configured to determine visibility for a geometry culling operation via the neural network hardware block, at least one core within the block of graphics cores configured to: provide geometry data for a scene to the neural network hardware block, the neural network block to perform neural network operations to detect an obstructed geometric object within the scene based on the geometry data;
receive a set of obstructed geometric objects for the scene from the neural network block; and cull the set of obstructed geometric objects from the scene.
Claims 3-20
Claims 2-8 and 10-20
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, and 11-18 are rejected under 35 U.S.C. 103 as being unpatentable over Umuroglu (US 20180039886 A1) in view of Ng (US 20190114533 A1), in view of Chen (US 10482565 B1), and further in view of Santodomingo (US 20040263512 A1).
Regarding to claim 1, Umuroglu discloses a graphics processor ([0019]: the neural networks classify incoming data sets, e.g., images; a programmable integrated circuit, FPGA and GPUs are graphic processor; Fig. 1; [0023]: a programmable integrated circuit; [0037]: the control circuit 130 loads a next set of binary weights and a next set of threshold values corresponding to a next layer of the binary neural network 101 into the memory circuit(s) 120 for use by the layer circuit(s) 120; [0039]: digital signal processing blocks; some FPGAs also include dedicated processor blocks; [0043]: a complete programmable processing system of microprocessors) comprising:
a block of graphics compute units ([0019]: a programmable integrated circuit, FPGA and GPUs include a block of graphic compute units; [0039]: digital signal processing blocks; some FPGAs also include dedicated processor blocks; [0043]: a complete programmable processing system of microprocessors); and
circuitry including a programmable neural network unit (Fig. 1; [0023]: a programmable integrated circuit includes a programmable binary neural network 101;
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Fig. 1; [0026]: the programmable hardware implementation of the binary neural network 101 includes layer circuits 120; Fig. 1; [0027]: the programmable IC 118 includes circuits to facilitate operation of the layer circuits 120; the programmable IC 118 also includes memory circuits 128 and a control circuit 130), the programmable neural network unit including one or more neural network hardware blocks (Fig. 1; [0026]: the programmable hardware implementation of the binary neural network 101 includes layer circuits 120; Fig. 1; [0027]: the programmable IC 118 includes circuits to facilitate operation of the layer circuits 120; the programmable IC 118 also includes memory circuits 128 and a control circuit 130; Fig. 2; [0028]: a layer circuit 120A of a neural network circuit;
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), wherein a neural network hardware block includes circuitry to perform neural network operations and activation operations for a layer of a neural network (Fig. 1; [0026]: the programmable hardware implementation of the binary neural network 101 includes layer circuits 120; the activations 108 are mapped to the output connections 126; [0027]: the programmable IC 118 includes circuits to facilitate operation of the layer circuits 120; Fig. 7; [0037]: using the programmable IC 118, the layer circuits 120 process the binary inputs thereto), wherein the programmable neural network unit is to configure one or more neural network hardware blocks (Umuroglu; [0021]: weights and thresholds are infrequently updated and configured; the weights and thresholds are configured to generate specialized hardware neurons; Fig. 1; [0023]: in a programmable integrated circuit, each layer 102 includes neurons 104 having inputs, and outputs; Fig. 3; [0030]: the count circuit 304 is configured to count the number of the X logic signals output by the XNOR circuit 302 that have a predefined logic state; Fig. 6; [0036]: in a the programmable IC 118, the layer circuit 120 is configured to implement the layer 102-1, then the layer 102-2, and so on until implementing the layer 102-n; the programmable IC 118 includes more than one layer circuit 120; Fig. 7; [0037]: using the programmable IC 118; the layer circuits 120 process the binary inputs thereto).
Umuroglu fails to explicitly disclose:
compute units are graphics cores; and
the programmable neural network unit addressable by cores within the block of graphics cores;
one or more neural network hardware blocks with a meta-shader neural network, the meta-shader neural network to generate a texture for one of multiple types of terrain.
In same field of endeavor, Ng teaches:
compute units are graphics cores ([0025]: a graphics processing unit; GPU; [0031]: GPU; Fig. 2; [0032]: the host 105 includes a processor 110 and a memory 115; the processor 110 represents any number of processing elements that each includes any number of processing cores; [0074]: assign additional processing cores in the host to execute the pre-processing stage; [0085]: graphics cards); and
the programmable neural network unit addressable by cores within the block of graphics cores ( Fig. 2; [0031]: the combination of interfacing a neural network accelerator 165, a neural network application, FPGA, and programmable logic is the programmable neural network unit; GPU and FPGA; Fig. 2; [0032]: the host 105 includes a processor 110 and a memory 115; the processor 110 represents any number of processing elements that each includes any number of processing cores; Fig. 2; [0033]: the memory 115 includes the neural network application 120 executed by the processor 110; the neural network application 120 establishes the neural network with any number of layers;
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);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Umuroglu to include compute units are graphics cores; and the programmable neural network unit addressable by cores within the block of graphics cores as taught by Ng. The motivation for doing so would have been to improve the performance of the neural network application; to increase the number of layers in the neural network 100; to execute the neural network application 120 by the processor 110 as taught by Ng in paragraphs [0006], [0030], and [0033].
Umuroglu in view of Ng fails to explicitly disclose:
one or more neural network hardware blocks with a meta-shader neural network, the meta-shader neural network to generate a texture for one of multiple types.
In same field of endeavor, Chen teaches:
one or more neural network hardware blocks with a meta-shader neural network (col. 2, lines 30-40: the multistage NN system may store neural networks as shader programs, i.e. meta-shader neural network, on a memory of a GPU; the weights of the neural networks are stored as shader objects or textures on the memory of the GPU; col. 5, lines 55-65: the multistage NN client 210 stores and executes shaders on the multistage NN server 117, which is configured to implement neural network shaders), the meta-shader neural network to generate a texture for one of multiple types of texture (col. 10, lines 20-30: the training engine 610 manages generating neural network models to generate weights which are stored as object data, e.g., texture data, on GPU memory; neural network models generate texture data; col. 11, lines 54-65: each neural network to be implemented has a shader program stored on the GPU and weights stored as texture data on the GPU; store the output as texture data; col. 12, lines 1-10: shader adds two input textures element by element and stores the result into the output texture; col. 13, lines 36-60: the shader engine 655 applies style transfer using a neural network to the head texture stored in the object memory 660; generate the modified texture; the modified texture is stored as a new texture).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Umuroglu in view of Ng to include one or more neural network hardware blocks with a meta-shader neural network, the meta-shader neural network to generate a texture for one of multiple types as taught by Chen. The motivation for doing so would have been to generate weights which are stored as object data, e.g., texture data, on GPU memory by neural network models; to store the output as texture data; to generate the modified texture by shader engine using a neural network as taught by Chen in col. 10, lines 20-30, col. 11, lines 54-65, and col. 13, lines 36-60.
Umuroglu in view of Ng and Chen fails to explicitly disclose: multiple types of texture are multiple types of terrain.
In same field of endeavor, Santodomingo teaches:
multiple types of texture are multiple types of terrain (Fig. 6; [0041]: various types of terrain classes; [0044]: a suburban terrain class is at a lower priority than an urban terrain class; two types of terrain; [0045]: the selected terrain class and another terrain class are different types; two types of terrain).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Umuroglu in view of Ng and Chen to include multiple types of texture are multiple types of terrain as taught by Santodomingo. The motivation for doing so would have been to improve rendering; to associate different types and sizes of scenery objects with each terrain class as taught by Santodomingo in paragraphs [0035], and [0045-0045].
Regarding to claim 2, Umuroglu in view of Ng, Chen, and Santodomingo discloses the graphics processor of claim 1, wherein the meta-shader neural network is to generate a texture for one of multiple types of texture based on one or more input parameters to the meta-shader neural network (Chen; col. 11, lines 54-65: each neural network to be implemented has a shader program stored on the GPU and weights stored as texture data on the GPU; store the output as texture data; col. 12, lines 1-10: shader adds two input textures element by element and stores the result into the output texture; col. 13, lines 36-60: the shader engine 655 applies style transfer using a neural network to the head texture stored in the object memory 660; generate the modified texture; the modified texture is stored as a new texture);
Umuroglu in view of Ng, Chen, and Santodomingo further discloses terrain (Santodomingo; Fig. 6; [0041]: various types of terrain classes; [0044]: a suburban terrain class is at a lower priority than an urban terrain class; two types of terrain; [0045]: the selected terrain class and another terrain class are different types; two types of terrain).
Same motivation of claim 1 is applied here.
Regarding to claim 3, Umuroglu in view of Ng, Chen, and Santodomingo discloses the graphics processor of claim 1, wherein the one or more neural network hardware blocks include a source data buffer, a neural network operations and activation operations block, and an output data buffer (Umuroglu; Fig. 1; [0027]: the programmable IC 118 includes circuits to facilitate operation of the layer circuits 120, including memory circuit(s) 128 and a control circuit 130; memory circuits 128 stores binary inputs and binary outputs for the layer circuits 120; Fig. 7; [0037]: the control circuit 130 loads a first set of binary weights and a first set of threshold values corresponding to a first layer of the binary neural network 101 into the memory circuits 128 for use by the layer circuits 120; the layer circuits 120 process the binary inputs thereto; the control circuit 130 stores the outputs of the layer circuits 120 in the memory circuits 128; the binary outputs of the layer circuits 120 are provided as the final outputs).
Regarding to claim 4, Umuroglu in view of Ng, Chen, and Santodomingo discloses the graphics processor of claim 3, wherein the neural network operations and activation operations block is programmably configurable (Umuroglu; [0021]: weights and thresholds are infrequently updated and configured; the weights and thresholds are configured to generate specialized hardware neurons; Fig. 1; [0023]: in a programmable integrated circuit, each layer 102 includes neurons 104 having inputs, and outputs; Fig. 3; [0030]: the count circuit 304 is configured to count the number of the X logic signals output by the XNOR circuit 302 that have a predefined logic state; Fig. 6; [0036]: in a the programmable IC 118, the layer circuit 120 is configured to implement the layer 102-1, then the layer 102-2, and so on until implementing the layer 102-n; the programmable IC 118 includes more than one layer circuit 120; Fig. 7; [0037]: using the programmable IC 118; the layer circuits 120 process the binary inputs thereto).
Regarding to claim 5, Umuroglu in view of Ng, Chen, and Santodomingo discloses the graphics processor of claim 4, wherein the programmable neural network unit includes a block programming unit (Umuroglu; Fig. 1; [0023]: a programmable integrated circuit; Fig. 1; [0026]: the programmable hardware implementation of the binary neural network 101 includes layer circuits 120) to configure layer state information for the one or more neural network hardware blocks (Umuroglu; [0021]: weights and thresholds are infrequently updated; the weights and thresholds are configured to generate specialized hardware neurons; Fig. 2; [0028]: data inputs of each of the hardware neurons 202 receive logic signals supplying binary inputs; the binary inputs are a set of the binary inputs 110 or a set of activations from a previous layer; receive X logic signals;
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; [0029]: each neuron 202 receives the same or a different set of binary weights.), the layer state information associated with one or more layers of a neural network to be processed by the programmable neural network unit (Umuroglu; [0021]: weights and thresholds are infrequently updated; the weights and thresholds are used to generate specialized hardware neurons; Fig. 1; [0023]: each neuron 104 supplies binary output 116 through an activation 108; [0029]: each neuron 202 receives the same or a different set of binary weights).
Regarding to claim 11, Umuroglu discloses a method ([0019]: the neural networks classify incoming data sets, e.g., images; a programmable integrated circuit, FPGA and GPUs are graphic processor; Fig. 1; [0023]: a programmable integrated circuit; [0037]: the control circuit 130 loads a next set of binary weights and a next set of threshold values corresponding to a next layer of the binary neural network 101 into the memory circuit(s) 120 for use by the layer circuit(s) 120; [0039]: digital signal processing blocks; some FPGAs also include dedicated processor blocks; [0043]: a complete programmable processing system of microprocessors; microprocessors are a graphics processor) comprising:
The rest claim limitations are similar to claim limitations recited in claim 1 and claim 2. Therefore, same rational used to reject claim 1 and claim 2 is also used to reject claim 11.
Regarding to claim 12, Umuroglu in view of Ng, Chen, and Santodomingo discloses the method of claim 11,
The claim limitations are similar to claim limitations recited in claim 3 and claim 4. Therefore, same rational used to reject claim 3 and claim 4 are also used to reject claim 12.
Regarding to claim 13, Umuroglu in view of Ng, Chen, and Santodomingo discloses the method of claim 12,
The claim limitations are similar to claim limitations recited in claim 5. Therefore, same rational used to reject claim 5 is also used to reject claim 13.
Regarding to claim 14, Umuroglu in view of Ng, Chen, and Santodomingo discloses the method of claim 13,
The rest claim limitations are similar to claim limitations recited in claim 8. Therefore, same rational used to reject claim 8 is also used to reject claim 14.
Regarding to claim 15, Umuroglu discloses a data processing system ([0019]: the neural networks classify incoming data sets, e.g., images; a programmable integrated circuit, FPGA and GPUs are graphic processor; Fig. 1; [0023]: a programmable integrated circuit; [0037]: the control circuit 130 loads a next set of binary weights and a next set of threshold values corresponding to a next layer of the binary neural network 101 into the memory circuit(s) 120 for use by the layer circuit(s) 120; [0039]: digital signal processing blocks; some FPGAs also include dedicated processor blocks; [0043]: a complete programmable processing system of microprocessors; microprocessors are a graphics processor) comprising:
a memory device (Fig. 1; [0027]: the programmable IC 118 includes circuits to facilitate operation of the layer circuits 120, and also includes memory circuits 128 and a control circuit 130); and
an accelerator device coupled with the memory device, the accelerator device includes a processing cluster and circuitry including a programmable neural network unit, the programmable neural network unit (Fig. 1; [0027]: the programmable IC 118 includes circuits to facilitate operation of the layer circuits 120, including memory circuits 128 and a control circuit 130;
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; Fig. 7; [0037]: the control circuit 130 loads a first set of binary weights and a first set of threshold values corresponding to a first layer of the binary neural network 101 into the memory circuit(s) 128 for use by the layer circuits 120), the graphics processor including :
the rest claim limitations are similar to claim limitations recited in claim 1. Therefore, same rational used to reject claim 1 is also used to reject claim 15.
Regarding to claim 16, Umuroglu in view of Ng, Chen, and Santodomingo discloses the data processing system of claim 15,
The rest claim limitations are similar to claim limitations recited in claim 3. Therefore, same rational used to reject claim 3 is also used to reject claim 16.
Regarding to claim 17, Umuroglu in view of Ng, Chen, and Santodomingo discloses the data processing system of claim 16,
The rest claim limitations are similar to claim limitations recited in claim 4. Therefore, same rational used to reject claim 4 is also used to reject claim 17.
Regarding to claim 18, Umuroglu in view of Ng, Chen, and Santodomingo discloses the data processing system of claim 17,
The rest claim limitations are similar to claim limitations recited in claim 5. Therefore, same rational used to reject claim 5 is also used to reject claim 18.
Claims 6-8 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Umuroglu (US 20180039886 A1) in view of Ng (US 20190114533 A1), in view of Chen (US 10482565 B1), in view of Santodomingo (US 20040263512 A1), and further in view of Vantrease (US 20190294959 A1).
Regarding to claim 6, Umuroglu in view of Ng, Chen, and Santodomingo discloses the graphics processor of claim 4, wherein the programmable neural network unit includes weights buffer to store weights associated with one or more layers of a neural network to be processed by the programmable neural network unit (Umuroglu; Fig. 3; [0027]: memory circuits 128 store binary inputs, binary weights, threshold values, and binary outputs for the layer circuits 120; [0029]: each neuron 202 receives the same or a different set of binary weights; Fig. 7; [0037]: loads a first set of binary weights and a first set of threshold values corresponding to a first layer of the binary neural network 101 into the memory circuits 128 for use by the layer circuit(s) 120).
Umuroglu in view of Ng, Chen, and Santodomingo fails to explicitly disclose weights cache and cache weights.
In same field of endeavor, Vantrease teaches weights cache and cache weights ([0045]: provide caching of data used for computations at computing engine 324; the data is cached at state buffer 322; the caching reduces the effect of memory access bottleneck; pre-fetch a set of weights to computing engine 324; Fig. 3A; [0047]: state buffer 322 may pre-fetch and cache a set of weights for one neural network layer; [0097]: field programmable gate arrays, i.e., FPGAs; level 1 (L1) caches, and level 2 (L2) caches).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Umuroglu in view of Ng, Chen, and Santodomingo to include weights cache and cache weights as taught by Vantrease. The motivation for doing so would have been to reduce the effect of memory access bottleneck on the performance of computing engine 324; to pre-fetch and cache a set of weights for one neural network layer as taught by Vantrease in paragraphs [0045] and [0047].
Regarding to claim 7, Umuroglu in view of Ng, Chen, Santodomingo, and Vantrease discloses the graphics processor of claim 6, wherein the programmable neural network unit includes multiple neural network hardware blocks (Umuroglu; Fig. 1; [0023]: a programmable integrated circuit (IC); the binary neural network includes one or more layers 102; each layer 102 includes neurons 104 having synapses 106, e.g., inputs, and activations 108,e.g., outputs; Fig. 1; [0026]: the hardware implementation of the binary neural network 101 includes layer circuits 120; each layer circuit 120 includes input connections 122, hardware neurons 124, and output connections 126; Fig. 1; [0027]: the programmable IC 118 includes circuits to facilitate operation of the layer circuit(s) 120, including memory circuit(s) 128 and a control circuit 130).
Regarding to claim 8, Umuroglu in view of Ng, Chen, Santodomingo, and Vantrease discloses the graphics processor of claim 7, wherein multiple neural network hardware blocks are respectively associated with one or more layers of the neural network to be processed by the programmable neural network unit (Umuroglu; Fig. 1; [0023]: a programmable integrated circuit (IC); the binary neural network includes one or more layers 102; each layer 102 includes neurons 104 having synapses 106, e.g., inputs, and activations 108, e.g., outputs; Fig. 6; [0036]: the binary neural network 101 includes n layers 102-1 through 102-n; Fig. 7; [0037]: using the programmable IC 118, the layer circuits 120 process the binary inputs thereto).
Regarding to claim 19, Umuroglu in view of Ng, Chen, and Santodomingo discloses the data processing system of claim 17,
The rest claim limitations are similar to claim limitations recited in claim 6. Therefore, same rational used to reject claim 6 is also used to reject claim 19.
Regarding to claim 20, Umuroglu in view of Ng, Chen, and Santodomingo discloses the data processing system of claim 19,
The rest claim limitations are similar to claim limitations recited in claim 7 and claim 8. Therefore, same rational used to reject claim 7 and claim 8 are also used to reject claim 20.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Umuroglu (US 20180039886 A1) in view of Ng (US 20190114533 A1), in view of Chen (US 10482565 B1), in view of Santodomingo (US 20040263512 A1), and further in view of Hakura (US 20190236829 A1).
Regarding to claim 9, Umuroglu in view of Ng, Chen, and Santodomingo discloses the graphics processor of claim 1, wherein the programmable neural network unit is to determine visibility for a geometry operation via the neural network hardware block and the neural network hardware block is to determine visibility on a per-object basis (Chen; col. 10, lines 35-55: the multistage NN server 117 comprises an interface engine 650, a shader engine 655, and an object memory 660; a fragment shader processes fragments, i.e. geometry operation, to generate one or more colors and a depth value, i.e. related to visibility, as fragment outputs; Vertex shaders are shaders in a render pipeline that render vertices of a scene; Fig. 12; col. 14, lines 33-45: once the shader processes of the multistage NN server 117 are complete, the interface engine 650 transmits the modified image 1200 to the display engine 625 for display;
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; the visibility is determined as illustrated in Fig. 12).
Umuroglu in view of Ng, Chen, and Santodomingo fails to explicitly disclose:
a geometry culling operation.
In same field of endeavor, Hakura teaches:
to determine visibility for a geometry culling operation and to determine visibility on a per-object basis ([0040]: image rendering operations; tessellation shader, vertex shader, geometry shader, and/or pixel/fragment shading programs; [0067]: the rasterizer 385 is configured to perform z culling and other z-based optimizations; [0072]: the graphics processing pipeline 320 includes cull, and clip unit (VPC); [0079]: the mesh shader 330 has culled all the graphics primitives processed by the mesh shader 330; [0100]: hierarchical culling; [0158]: the graphics processing pipeline performs primitive culling operations; [0177]: the second plurality of execution threads performs one or more culling operations on a plurality of graphics primitives specified via the first indirect index buffer and the first vertex buffer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Umuroglu in view of Ng, Chen, and Santodomingo to include to determine visibility for a geometry culling operation and to determine visibility on a per-object basis as taught by Hakura. The motivation for doing so would have been perform z culling and other z-based optimizations; to perform primitive culling operations as taught by Hakura in paragraphs [0067] and [0158].
Regarding to claim 10, Umuroglu in view of Ng, Chen, and Santodomingo discloses the graphics processor of claim 1, further comprising to configure the programmable neural network unit (Umuroglu; [0021]: weights and thresholds are infrequently updated; the weights and thresholds are used to generate specialized hardware neurons; Fig. 1; [0023]: in a programmable integrated circuit, i.e. programmable IC, each layer 102 includes neurons 104 having synapses 106, e.g., inputs, and activations 108, e.g., outputs; Fig. 6; [0036]: in a the programmable IC 118, the layer circuit 120 is configured to implement the layer 102-1, then the layer 102-2, and so on until implementing the layer 102-n; the programmable IC 118 includes more than one layer circuit 120; Fig. 7; [0037]: using the programmable IC 118; the layer circuit(s) 120 process the binary inputs thereto).
Umuroglu in view of Ng, Chen, and Santodomingo fails to explicitly disclose:
a tessellation module to generate tessellated output based on coarse input data.
In same field of endeavor, Hakura teaches a tessellation module to generate tessellated output based on coarse input data ([0040]: image rendering operations include tessellation shader, vertex shader, geometry shader, and/or pixel/fragment shading programs, general compute operations, etc.; [0094]: the task shader 650 performs read/load operations, general compute operations, vertex shading operations, tessellation operations, geometry shading operations, and write/store operations; [0100]: programmable tessellation patterns).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Umuroglu in view of Ng, Chen, and Santodomingo to include a tessellation module to generate tessellated output based on coarse input data as taught by Hakura. The motivation for doing so would have been perform z culling and other z-based optimizations; to perform primitive culling operations as taught by Hakura in paragraphs [0067] and [0158].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hai Tao Sun whose telephone number is (571)272-5630. The examiner can normally be reached 9:00AM-6:00PM.
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/HAI TAO SUN/Primary Examiner, Art Unit 2616
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