DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 1/9/2025 have been accepted by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KANG et al. [US 2020/0327063].
Claim 1, KANG et al. discloses a memory system [Fig 2, 110], comprising: one or more memory devices [Fig. 2,150]; and processing circuitry coupled with the one or more memory devices [Fig 2, controller 130] and configured to cause the memory system to: receive a read command [the controller 130 may control the memory device 150 in response to a request from the host 102 such as read operations, par. 0111] comprising a logical address that is associated with data stored to a physical address of a non-volatile memory array of the memory system [par. 0063]; transfer, from the non-volatile memory array to a volatile memory array of the memory system, a first portion of an address mapping based at least in part on receiving the read command [par. 0064], wherein the first portion of the address mapping is associated with a counter and includes a mapping between the logical address of the read command and the physical address of the non-volatile memory array [par. 0065-0066]; determine whether a first value of the counter matches a second value that is stored to the non-volatile memory array of the memory system based at least in part on transferring the first portion of the address mapping from the non-volatile memory array to the volatile memory array [par. 0067]; and verify that the first portion of the address mapping comprises a first version based at least in part on determining that the first value matches the second value [comparing of actual address with address mapped, par. 0136].
Claim 2, KANG et al. discloses the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: identify a trigger condition for storing the transferred first portion of the address mapping to a portion of the non-volatile memory array [par. 0138, par. 0300]; increment the counter to a third value based at least in part on identifying the trigger condition […may adjust count, par. 0138 and 0302]; and store the first portion of the address mapping to the portion of the non-volatile memory array based at least in part on incrementing the counter to the third value [par. 0138, …provide the memory map segment stored in the memory device 150 to the host cache 106 based on the read count threshold of the memory map segment].
Claim 3, KANG et al. discloses the memory system of claim 2, wherein the trigger condition comprises receiving a flush command, determining that a quantity of write operations has satisfied a first threshold, determining that a storage capacity of a volatile memory of the memory system has satisfied a second threshold, or any combination thereof [par. 0139, the number of dirty cache blocks of the MM 44 exceeds a specific threshold value].
Claim 4, KANG et al. discloses the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: transmit an indication to a host system that the read command was not satisfied based at least in part on determining that the first value is different than the second value [par. 0201-0204].
Claim 5, KANG et al. discloses the memory system of claim 4, wherein the processing circuitry is further configured to cause the memory system to: perform a reset of the memory system based at least in part on transmitting the indication to the host system; and transfer, for a second time, the first portion of an address mapping from the non-volatile memory array to the volatile memory array based at least in part on performing the reset of the memory system [par. 0678].
Claim 6, KANG et al. discloses the memory system of claim 5, wherein the processing circuitry is further configured to cause the memory system to: receive a second read command [second operation, par. 0264 and 0273] comprising the logical address that is associated with data stored to the physical address of the non-volatile memory array of the memory system [par. 0065-0066]; determine that first value of the counter matches the second value based at least in part on receiving the second read command and transferring the first portion of the address mapping from the non-volatile memory array to the volatile memory array for the second time [par. 0067]; and transmit the data to the host system based at least in part on determining that the first value of the counter matches the second value [comparing of actual address with address mapped, par. 0136].
Claim 7, KANG et al. discloses the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: read the data from the physical address of the non-volatile memory array corresponding to the logical address based at least in part on determining that the first value of the counter matches the second value [par. 0066].
Claim 8, KANG et al. discloses the memory system of claim 1, wherein determining whether the first value matches the second value comprises the processing circuitry configured to cause the memory system to: compare the first value of the counter with the second value, wherein the second value is associated with a version of the first portion of the address mapping [comparing of actual address with address mapped, par. 0136].
Claim 9, KANG et al. discloses the memory system of claim 1, wherein: the first value is indicated by metadata associated with a set of mappings included in the first portion of the address mapping, and the set of mappings comprises the logical address and the physical address [par. 0136].
Claim 10, KANG et al. the memory system of claim 1, wherein the first value is indicated by a field associated with the first portion of the address mapping [address stored in OOB are of each page, par. 0136].
Claim 11, KANG et al. discloses the memory system of claim 1, wherein the first portion of the address mapping comprises a second version based at least in part on the first value being different than the second value [par. 0136 wherein the comparison could show that they are different].
Claim 12, KANG et al. discloses the memory system of claim 11, wherein the first version comprises an up-to-date version of the first portion of the address mapping and the second version comprises an out-of-date version of the first portion of the address mapping [see par. 0136].
Claims 13-23 and 24-25 are rejected using the same rationale as claims 1-12 above.
Response to Arguments
Applicant's arguments filed 7/1/2026 have been fully considered but they are not persuasive. Under broadest reasonable interpretation, the limitations of the independent claims do not restrict the claimed matches strictly to mathematical equality nor does it require specialized versions of architecture beyond functional verification. Kang discloses maintaining a read count associated with a map segment and determining if it satisfies a stored reference threshold in the memory system [Kang par. 0066-0067 and 0300-0302]. This teaching meets the limitation of determining if a first counter value matches a second stored value. Kang teaches tracking and verifying versions of data and map updates [Kang 0136 and 0140]. Applicant’s argument improperly reads narroy operational limitations from the specification into the claims. Because Kang discloses each recited feature, the rejection of the claims is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MIDYS ROJAS/ Primary Examiner, Art Unit 2133
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