DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/10/2025 was considered by the examiner.
Drawings
The drawings received on 1/10/2025 have been accepted by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims recite elements and operations such as generating an address mask table, attaching a call wrapper, identifying a transition process, replacing the transition process, allocating memory, assigning addresses, and unmasking an address. These elements and operations represent data manipulation, program modifications, and address translation operations which fall within the category of mathematical concepts and mental processes and as such, the claims are directed to abstract ideas. See par. 0058-0069 for support. This judicial exception is not integrated into a practical application because the claims merely mention the use of a generic processing circuit and not a specialized processor, the claims do not integrate the abstract elements into a practical application and the claimed steps do not impose any limits on the abstract ideas. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nashimoto [US 2023/0334149].
Claim 1, Nashimoto discloses a program processing device comprising processing circuitry [Fig .1 and par. 0026-0033] to generate an address mask table about a program or a memory used by the program based on setting data which specifies a physical address and a logical address [see par. 0076-0087 and par. 0114-0129 and 0134], to attach to the program a call wrapper being a function that performs context switch [par. 0172-0189]; to identify a transition process of performing the context switch from the program; and to replace the transition process with a process of performing a jump by specifying a physical address where the call wrapper is to be deployed [par. 0138-0139, 0256-0263], and to look up the address mask table, in executing a countermeasure-applied program, so as to allocate a memory and to assign a physical address [par. 0141-0145; 0147-0152]; and instead of acquiring a jump address with no change in the transition process, to make a change so as to use a jump address obtained by unmasking the jump address acquired by looking up the address mask table, based on determined isolation setting [par. 0147-0156, -175-0189].
Claim 2, Nashimoto discloses the program processing device according to The program processing device according to wherein the processing circuitry generates the address mask table with a plurality of combinations by the program by varying the physical address and the logical address about the program or the memory used by the program [see par. 0084-0087 and 0126-0129].
Claim 3, Nashimoto discloses the program processing device according to The program processing device according to wherein the processing circuitry adds a link process of the call wrapper instead of statically attaching the call wrapper before executing the program [par. 0256-0259], and when executing the program, executes the link process which is dynamic, thereby linking the call wrapper [par. 0260-0263].
Claim 4, Nashimoto discloses the program processing device according to The program processing device according to 2 wherein the processing circuitry adds a link process of the call wrapper instead of statically attaching the call wrapper before executing the program, and when executing the program, executes the link process which is dynamic, thereby linking the call wrapper [see par. 0084-0087 and 0256-0263].
Claim 5, Nashimoto discloses the program processing device according to Claim 1 wherein the processing circuitry generates the address mask table as a hash table [see par. 0114-0134 and 0076-0087].
Claim 6, Nashimoto discloses the program processing device according to Claim 2 wherein the processing circuitry generates the address mask table as a hash table [see par. 0114-0134 and 0076-0087].
Claim 7, Nashimoto discloses the program processing device according to Claim 3 wherein the processing circuitry generates the address mask table as a hash table [see par. 0114-0134 and 0076-0087].
Claim 8, Nashimoto discloses the program processing device according to Claim 4 wherein the processing circuitry generates the address mask table as a hash table [see par. 0114-0134 and 0076-0087].
Claim 9 is rejected using the same rationale as Claim 1.
Claim 10 is rejected using the same rationale as Claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nashimoto [US 12,259,966]; Program Processing Device and Program Processing Method that Executes a Mask Process on an Entry Address Used by an Application Program. See Abstract.
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/MIDYS ROJAS/Primary Examiner, Art Unit 2133