Prosecution Insights
Last updated: July 05, 2026
Application No. 19/016,130

IN-MEMORY PROCESSOR AND MEMORY DEVICE INCLUDING THE IN-MEMORY PROCESSOR

Non-Final OA §101§102§112
Filed
Jan 10, 2025
Priority
Jul 18, 2024 — RE 10-2024-0095143
Examiner
CYGIEL, GARY W
Art Unit
2137
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
1y 10m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
412 granted / 540 resolved
+21.3% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
13 currently pending
Career history
559
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
62.7%
+22.7% vs TC avg
§102
22.4%
-17.6% vs TC avg
§112
10.0%
-30.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 540 resolved cases

Office Action

§101 §102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 19 and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites an in memory processor performing a calculation based on information in a first location among plural locations and, further, changing a rule as to which location to choose based on an external command. This is analogous to a human solving an odd set of math problems and then solving the even set in response to an instruction from a professor. This judicial exception is not integrated into a practical application because it does not impose meaningful limits on practicing an abstract idea. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements of using generically recited computing components to perform the listed steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The additional limitations of the remaining claims are directed towards common computing elements and introduce variables associated with these components (i.e., storing plural rules (i.e., index cards with different problem sets) and plural access keys (i.e., an index card identifier)), but they still represent an abstract idea embodied in a generic computer that performs a method that could be done by a human without the aid of a computer. For at least these reasons, the claims are not patent eligible. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 19 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by KIM et al. (US PGPub No. 2024/0403053), hereinafter referred to as KIM. Consider Claim 19, KIM teaches a memory device configured to perform a calculation operation (KIM, e.g., Fig 3, PIM device.), comprising: an in-memory processor configured to perform the calculation operation based on a target calculation register of a plurality of calculation registers (KIM, e.g., Fig 3(120), PIM engine; ¶0039, registers of the PIM engine are small and fast storage elements that temporarily store data and PIM operands during the PIM operation (i.e., calculation).); and a control logic circuit configured to change a register indexing rule used to determine the target calculation register in response to a command provided from an external device (KIM, e.g., ¶0051, addressing mode selection unit may select an indirect or direct addressing mode (i.e., a register indexing rule) according to a result of decoding the PIM instruction.). Allowable Subject Matter Claims 1 and 11 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: The prior art discloses PIM systems including a register array (KIM, e.g., Fig 3(120) and teaches logic to change a register indexing rule used to determine the target calculation register (KIM, e.g., ¶0051), and an instruction list circuit to store a first instruction (KIM, e.g., Fig 3(5), command latch.). Therefore, the primary reason for the indication of allowable subject matter, is the inclusion of the specific in-memory processing details wherein Claim 1 includes a processing management circuit configured to store a register indexing rule table and an address log, wherein the register indexing rule table comprises a first register indexing rule that corresponds to a value of the first register indexing field, and wherein the processing management circuit is configured to identify a first calculation register of the plurality of calculation registers based on the first register indexing rule and the address log, and Claim 11 details determining plural register indices based on plural register index rules, wherein the register index for the same instruction changes, in combination with the other elements recited, which is not found or fairly obviated by the prior art of record. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Gary W. Cygiel/Primary Examiner, Art Unit 2137
Read full office action

Prosecution Timeline

Jan 10, 2025
Application Filed
Apr 22, 2026
Non-Final Rejection mailed — §101, §102, §112
May 20, 2026
Applicant Interview (Telephonic)
May 28, 2026
Examiner Interview Summary

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
86%
With Interview (+9.3%)
3y 4m (~1y 10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 540 resolved cases by this examiner. Grant probability derived from career allowance rate.

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