DETAILED ACTION
Status of Claims
The status of the claims is as follows:
(a) Claims 1-20 remain pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The Applicant claims benefit of a prior-filed application under 35 U.S.C. §119(e) or under 35 U.S.C. §120, §121, §365(c), or §386(c).
Information Disclosure Statement
The Information Disclosure Statement(s) (IDS) filed on 03/11/2025; 08/19/2025; and 10/15/2025 comply with the provisions of 37 C.F.R. §1.97 and §1.98. The Examiner has considered all references, except for any references lined through on the attached IDS form.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. A claim is indefinite when it contains words or phrases whose meaning is unclear.
(a) Regarding Claim 16, the term “the first slot” lacks antecedent basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Renard et al. U.S. P.G. Publication 2019/0288155 A1 (hereinafter, Renard), in view of Hu et al. U.S. P.G. Publication 2019/0326207 A1 (hereinafter, Hu).
Regarding Claim 1, Renard describes a packaging structure comprising:
-a substrate module comprising a substrate (substrate, Renard, Paragraphs 0015–0016 and Figures 1A–1D); …
-and a light emitting unit and a light receiving unit located on the substrate (light-emitting device and image sensor die located on a substrate, Renard, Paragraphs 0015, 0017, and 0020 and Figures 1A–1D), the light receiving unit comprising a photosensitive area and a non-photosensitive area connected to the photosensitive area (image sensor and active surface including electrical circuitry of image sensor die, Renard, Paragraphs 0018 and 0026 and Figures 1A–1D); …
Renard does not specifically describe the substrate module defining a plurality of first hollow conductive channels and a plurality of second hollow conductive channels; wherein each of the plurality of first hollow conductive channels comprises a first channel and a first conductive layer formed on an inner wall of the first channel, two ends of the first channel extend to the substrate and the non-photosensitive area, respectively, each of the plurality of first hollow conductive channels is electrically connected to the substrate and the non-photosensitive area; each of the plurality of second hollow conductive channels comprises a second channel and a second conductive layer formed on an inner wall of the second channel, two ends of the second channel extend to the substrate and the light emitting unit, respectively, and the plurality of second hollow conductive channels is electrically connected to the substrate and the light emitting unit.
Hu discloses, teaches, or at least suggests the missing limitations. Hu discloses connection through holes extending between substrate circuitry and respective device pins, with conductive material bonded to the inner walls of the connection through holes and the respective device pins to form conductive layers electrically connecting the devices to the substrate (Hu, Paragraphs 0073 and 0076–0077 and Figures 4 and 9).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard to include the substrate module defining a plurality of first hollow conductive channels and a plurality of second hollow conductive channels; wherein each of the plurality of first hollow conductive channels comprises a first channel and a first conductive layer formed on an inner wall of the first channel, two ends of the first channel extend to the substrate and the non-photosensitive area, respectively, each of the plurality of first hollow conductive channels is electrically connected to the substrate and the non-photosensitive area; each of the plurality of second hollow conductive channels comprises a second channel and a second conductive layer formed on an inner wall of the second channel, two ends of the second channel extend to the substrate and the light emitting unit, respectively, and the plurality of second hollow conductive channels is electrically connected to the substrate and the light emitting unit, as disclosed, taught, or at least suggested by Hu.
It would have been obvious to combine and modify the cited references to electrically connect the devices to the substrate using conductive layers formed along inner walls of connection through holes because such connections reduce the overall package volume while providing stable electrical connections between the devices and substrate circuitry (Hu, Paragraphs 0030–0031).
Regarding Claim 10, Renard describes a preparation method of a packaging structure comprising:
-forming a light receiving unit and a light emitting unit on a substrate of a substrate module, wherein the light receiving unit comprises a photosensitive area and a non-photosensitive area connected to the photosensitive area (forming light-emitting device and image sensor die including image sensor on a substrate, Renard, Paragraphs 0037–0040 and Figures 2A–2C); …
Renard does not specifically describe defining a plurality of first channels and a plurality of second channels in the substrate module, wherein two ends of each of the plurality of first channels extend to the substrate and the non-photosensitive area, respectively, and two ends of each of the plurality of second channels extend to the substrate and the light emitting unit, respectively; and forming a first conductive layer on an inner wall of each of the plurality of first channels to form a first hollow conductive channel, and forming a second conductive layer on an inner wall of each of the plurality of second channels to form a second hollow conductive channel, wherein the first hollow conductive channel is electrically connected to the substrate and the non-photosensitive area, and the second hollow conductive channel is electrically connected to the substrate and the light emitting unit, thereby obtaining the packaging structure.
Hu discloses, teaches, or at least suggests the missing limitations. Hu discloses forming connection through holes through a substrate to respective device pins and forming conductive material along the inner walls of the connection through holes to form conductive layers electrically connecting the devices to substrate circuitry (Hu, Paragraphs 0073 and 0076–0077 and Figures 4 and 9).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard to include defining a plurality of first channels and a plurality of second channels in the substrate module, wherein two ends of each of the plurality of first channels extend to the substrate and the non-photosensitive area, respectively, and two ends of each of the plurality of second channels extend to the substrate and the light emitting unit, respectively; and forming a first conductive layer on an inner wall of each of the plurality of first channels to form a first hollow conductive channel, and forming a second conductive layer on an inner wall of each of the plurality of second channels to form a second hollow conductive channel, wherein the first hollow conductive channel is electrically connected to the substrate and the non-photosensitive area, and the second hollow conductive channel is electrically connected to the substrate and the light emitting unit, thereby obtaining the packaging structure, as disclosed, taught, or at least suggested by Hu.
It would have been obvious to combine and modify the cited references to electrically connect the devices to the substrate using conductive layers formed along inner walls of connection through holes because such connections reduce the overall package volume while providing stable electrical connections between the devices and substrate circuitry (Hu, Paragraphs 0030–0031).
Regarding Claim 17, Renard, as modified, describes the preparation method of claim 10.
Renard does not specifically describe wherein forming the first conductive layer and the second conductive layer further comprises: forming a conductive material on the inner wall of each of the plurality of first channels and inner wall of each of the plurality of second channels; and solidify the conductive material to form the first conductive layer and the second conductive layer.
Hu discloses, teaches, or at least suggests the missing limitations. Hu discloses forming conductive material along the inner walls of connection through holes and heat treating the conductive material to form mechanical and electrical connections (Hu, Paragraph 0077 and Figures 4 and 9).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard to include wherein forming the first conductive layer and the second conductive layer further comprises: forming a conductive material on the inner wall of each of the plurality of first channels and inner wall of each of the plurality of second channels; and solidify the conductive material to form the first conductive layer and the second conductive layer, as disclosed, taught, or at least suggested by Hu.
It would have been obvious to combine and modify the cited references to form and solidify conductive material on the inner walls of the channels because the conductive material is applied within the connection through holes and heat treated to form the electrical connections (Hu, Paragraph 0077).
Claims 2, 8, 11, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Renard, in view of Hu, further in view of Dutta U.S. P.G. Publication 2005/0224946 A1 (hereinafter, Dutta).
Regarding Claim 2, Renard, as modified, describes the packaging structure of claim 1, wherein the light emitting unit comprises a driving chip and a light source located on the driving chip, the driving chip is electrically connected to the light source (VCSEL chip 162C or 162B bonded on driver chip by solder connecting driver chip contacts, Dutta, Paragraphs 0120–0121 and Figures 25A–25C); …
Renard does not specifically describe the substrate module further comprises a plastic encapsulation body, the substrate comprises a first surface and a second surface opposite to each other, each of the plastic encapsulation body, the light receiving unit, and the driving chip is located on a same surface of the first surface and the second surface, the plastic encapsulation body is at least adhered to sidewalls of the light receiving unit and the driving chip, and each of the plurality of second hollow conductive channels is electrically connected to the substrate and the driving chip.
Hu discloses, teaches, or at least suggests the missing limitations. Hu discloses an encapsulation layer encapsulating and fixing multiple devices on a substrate and connection through holes having conductive layers electrically connecting device pins to substrate circuitry (Hu, Paragraphs 0041, 0075–0077, and 0082 and Figures 4 and 9).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard to include the substrate module further comprises a plastic encapsulation body, the substrate comprises a first surface and a second surface opposite to each other, each of the plastic encapsulation body, the light receiving unit, and the driving chip is located on a same surface of the first surface and the second surface, the plastic encapsulation body is at least adhered to sidewalls of the light receiving unit and the driving chip, and each of the plurality of second hollow conductive channels is electrically connected to the substrate and the driving chip, as disclosed, taught, or at least suggested by Hu.
It would have been obvious to combine and modify the cited references to encapsulate the devices on the substrate and electrically connect the driving chip to the substrate through the conductive channels because the encapsulation protects and fixes the devices while the conductive channels provide stable electrical connections in a reduced package volume (Hu, Paragraphs 0030–0031, 0041, and 0075).
Regarding Claim 8, Renard, as modified, describes the packaging structure of claim 2.
Renard does not specifically describe further comprising a plurality of electronic components, wherein the plurality of electronic components is embedded in the plastic encapsulation body, or located out of the plastic encapsulation body, or located on the substrate.
Hu discloses, teaches, or at least suggests the missing limitations. Hu discloses packaging chips together with electronic devices including resistors, capacitors, inductors, diodes, and transistors on the substrate and within the encapsulation structure (Hu, Paragraphs 0047 and 0081–0082).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard to include a plurality of electronic components, wherein the plurality of electronic components is embedded in the plastic encapsulation body, or located out of the plastic encapsulation body, or located on the substrate, as disclosed, taught, or at least suggested by Hu.
It would have been obvious to combine and modify the cited references to package additional electronic components with the optical devices because the components can be packaged using the same equipment and process flow to increase efficiency and reduce cost (Hu, Paragraphs 0047 and 0081–0082).
Regarding Claim 11, Renard, as modified, describes the preparation method of claim 10, wherein the light emitting unit comprises a driving chip and a light source located on the driving chip (VCSEL chip 162C or 162B bonded on driver chip, Dutta, Paragraphs 0120–0121 and Figures 25A–25C); …
Renard does not specifically describe wherein the substrate module further comprises a plastic encapsulation body, the substrate comprises a first surface and a second surface opposite to each other, the plastic encapsulation body, the light receiving unit, and the driving chip are located on one of the first surface and the second surface, and the plastic encapsulation body is at least adhered to sidewalls of the driving chip and the light receiving unit, and further located between the driving chip and the light receiving unit.
Hu discloses, teaches, or at least suggests the missing limitations. Hu discloses providing an encapsulation layer on a substrate to encapsulate and fix multiple devices positioned on the substrate (Hu, Paragraphs 0041, 0075, and 0082).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard to include wherein the substrate module further comprises a plastic encapsulation body, the substrate comprises a first surface and a second surface opposite to each other, the plastic encapsulation body, the light receiving unit, and the driving chip are located on one of the first surface and the second surface, and the plastic encapsulation body is at least adhered to sidewalls of the driving chip and the light receiving unit, and further located between the driving chip and the light receiving unit, as disclosed, taught, or at least suggested by Hu.
It would have been obvious to combine and modify the cited references to encapsulate the devices together on the substrate because the encapsulation protects the devices and fixes their relative positions to provide stable electrical connections (Hu, Paragraphs 0041 and 0075).
Regarding Claim 15, Renard, as modified, describes the preparation method of claim 11.
Renard does not specifically describe wherein the plurality of first channels and the plurality of second channels are located on the substrate.
Hu discloses, teaches, or at least suggests the missing limitations. Hu discloses connection through holes formed in the substrate and conductive layers formed along the inner walls of the connection through holes (Hu, Paragraphs 0069, 0073, and 0076–0077 and Figures 4 and 9).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard to include wherein the plurality of first channels and the plurality of second channels are located on the substrate, as disclosed, taught, or at least suggested by Hu.
It would have been obvious to combine and modify the cited references to locate the channels in the substrate because the connection through holes provide electrical connections between devices mounted on the substrate and the substrate circuitry (Hu, Paragraphs 0069 and 0073).
Regarding Claim 19, Renard, as modified, describes the preparation method of claim 11.
Renard does not specifically describe further comprising: providing a board comprising a plurality of substrates arranged in arrays, wherein adjacent two of the plurality of substrates form a cutting area therebetween; fabricating each of the plurality of substrates into a package unit, wherein the package unit comprises one of the plurality of substrates, the driving chip, and the plastic encapsulation body, the light emitting unit, and the light receiving unit located on the one of the plurality of substrates; and forming the first conductive layer and the second conductive layer in the package unit to form the first hollow conductive channel and the second hollow conductive channel, respectively, and cutting the board along the cutting area to obtain a plurality of packaging structures.
Hu discloses, teaches, or at least suggests the missing limitations. Hu discloses mounting a plurality of devices on a large substrate for batch processing and, after packaging, cutting the substrate into a plurality of sub-boards according to a predetermined grouping (Hu, Paragraph 0078).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard to include further comprising: providing a board comprising a plurality of substrates arranged in arrays, wherein adjacent two of the plurality of substrates form a cutting area therebetween; fabricating each of the plurality of substrates into a package unit, wherein the package unit comprises one of the plurality of substrates, the driving chip, and the plastic encapsulation body, the light emitting unit, and the light receiving unit located on the one of the plurality of substrates; and forming the first conductive layer and the second conductive layer in the package unit to form the first hollow conductive channel and the second hollow conductive channel, respectively, and cutting the board along the cutting area to obtain a plurality of packaging structures, as disclosed, taught, or at least suggested by Hu.
It would have been obvious to combine and modify the cited references to fabricate multiple package units together on a larger substrate and subsequently cut the substrate into separate package units because batch processing reduces packaging cost and saves packaging time (Hu, Paragraph 0078).
Claims 3-5 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Renard, in view of Hu, further in view of Dutta, and further in view of Yap et al. U.S. P.G. Publication 2014/0264945 A1 (hereinafter, Yap).
Regarding Claim 3, Renard, as modified, describes the packaging structure of claim 2, wherein the driving chip and the light receiving unit are located on the first surface (image sensor die and light-emitting device located on first surface, Renard, Paragraphs 0017 and 0020 and Figures 1A-1D); …
Renard does not specifically describe the first channel and the second channel are defined in the plastic encapsulation body; the first channel comprises a first portion, a second portion, and a third portion connected to the first portion and the second portion, each of the first portion and the second portion extends along a thickness direction of the packaging structure, one end of the first portion is connected to the substrate, and one end of the second portion is connected to the non-photosensitive area.
Yap discloses, teaches, or at least suggests the missing limitations. Yap discloses conductive paths formed along molded package layers in a stair-step configuration having vertical conductive portions connected by a conductive run portion extending across a major surface (Yap, Paragraph 0038 and Figures 8–9 and 16).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard to include the first channel and the second channel are defined in the plastic encapsulation body; the first channel comprises a first portion, a second portion, and a third portion connected to the first portion and the second portion, each of the first portion and the second portion extends along a thickness direction of the packaging structure, one end of the first portion is connected to the substrate, and one end of the second portion is connected to the non-photosensitive area, as disclosed, taught, or at least suggested by Yap.
It would have been obvious to combine and modify the cited references to provide the conductive path in a stair-step configuration because the configuration electrically connects components located at different package levels using vertical conductive portions connected by a conductive run portion (Yap, Paragraph 0038 and Figure 16).
Regarding Claim 4, Renard, as modified, describes the packaging structure of claim 3.
Renard does not specifically describe wherein the plastic encapsulation body comprises a first plastic encapsulation block and a second plastic encapsulation block located on the first plastic encapsulation block, the first plastic encapsulation block is adhered to the sidewalls of the light receiving unit and the driving chip, the second plastic encapsulation block covers a portion of the non-photosensitive area and a portion of a top surface of the driving chip, the first portion extends through the first plastic encapsulation block and the second plastic encapsulation block, the second portion extends through the second plastic encapsulation block, and the third portion is exposed from the second plastic encapsulation block.
Yap discloses, teaches, or at least suggests the missing limitations. Yap discloses first and second molded package layers positioned in a stacked relationship, with encapsulant covering embedded devices and stair-step conductive portions extending along the respective package levels (Yap, Paragraphs 0022, 0029–0030, and 0038 and Figures 2, 6–9, and 16).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard to include wherein the plastic encapsulation body comprises a first plastic encapsulation block and a second plastic encapsulation block located on the first plastic encapsulation block, the first plastic encapsulation block is adhered to the sidewalls of the light receiving unit and the driving chip, the second plastic encapsulation block covers a portion of the non-photosensitive area and a portion of a top surface of the driving chip, the first portion extends through the first plastic encapsulation block and the second plastic encapsulation block, the second portion extends through the second plastic encapsulation block, and the third portion is exposed from the second plastic encapsulation block, as disclosed, taught, or at least suggested by Yap.
It would have been obvious to combine and modify the cited references to form stacked molded package levels with conductive portions extending between the package levels because the configuration permits devices at different package levels to be electrically interconnected within a compact package (Yap, Paragraphs 0029-0030 and 0038 and Figures 6-9 and 16).
Regarding Claim 5, Renard, as modified, describes the packaging structure of claim 4.
Renard does not specifically describe further comprising a protective film, wherein the protective film is formed on the second plastic encapsulation block and covers the third portion.
Yap discloses, teaches, or at least suggests the missing limitations. Yap discloses an overlying dielectric, capping, or passivation layer formed over package conductors (Yap, Paragraph 0025 and Figure 4).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard to include a protective film, wherein the protective film is formed on the second plastic encapsulation block and covers the third portion, as disclosed, taught, or at least suggested by Yap.
It would have been obvious to combine and modify the cited references to cover the exposed conductive portion with a dielectric, capping, or passivation layer to protect the conductive package structure (Yap, Paragraph 0025 and Figure 4).
Regarding Claim 12, Renard, as modified, describes the preparation method of claim 11.
Renard does not specifically describe wherein the plurality of first channels and the plurality of second channels are located on the plastic encapsulation body.
Yap discloses, teaches, or at least suggests the missing limitations. Yap discloses cavities and conductive paths formed along molded package bodies to electrically interconnect microelectronic devices contained in the package layers (Yap, Paragraphs 0037–0038 and Figures 8–9 and 14–16).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard to include wherein the plurality of first channels and the plurality of second channels are located on the plastic encapsulation body, as disclosed, taught, or at least suggested by Yap.
It would have been obvious to combine and modify the cited references to locate the conductive channels on the molded package body because the arrangement provides electrical interconnection between devices contained within the molded package layers (Yap, Paragraphs 0037-0038 and Figures 14-16).
Regarding Claim 13, Renard, as modified, describes the preparation method of claim 12.
Renard does not specifically describe wherein forming the light emitting unit and the light receiving unit on the substrate comprises: forming a second plastic encapsulation block on the non-photosensitive area of the light receiving unit and the driving chip; installing the light receiving unit and the driving chip with the second plastic encapsulation block on the first surface, wherein the substrate further comprises a plastic encapsulation preform thereon, and the plastic encapsulation preform is at least adhered to sidewalls of the light receiving unit and the driving chip; and solidifying the plastic encapsulation preform to obtain a first plastic encapsulation block, wherein the first plastic encapsulation block and the second plastic encapsulation block form the plastic encapsulation body.
Yap discloses, teaches, or at least suggests the missing limitations. Yap discloses positioning devices within encapsulant, solidifying the encapsulant to form molded package layers, and positioning first and second molded package layers in a stacked relationship (Yap, Paragraphs 0022 and 0029-0030 and Figures 2 and 6–7).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard to include wherein forming the light emitting unit and the light receiving unit on the substrate comprises: forming a second plastic encapsulation block on the non-photosensitive area of the light receiving unit and the driving chip; installing the light receiving unit and the driving chip with the second plastic encapsulation block on the first surface, wherein the substrate further comprises a plastic encapsulation preform thereon, and the plastic encapsulation preform is at least adhered to sidewalls of the light receiving unit and the driving chip; and solidifying the plastic encapsulation preform to obtain a first plastic encapsulation block, wherein the first plastic encapsulation block and the second plastic encapsulation block form the plastic encapsulation body, as disclosed, taught, or at least suggested by Yap.
It would have been obvious to combine and modify the cited references to form the encapsulation body from solidified stacked molded package layers because the stacked package arrangement permits embedded devices to be packaged and interconnected in a compact multilayer structure (Yap, Paragraphs 0022 and 0029-0030 and Figures 2 and 6-7).
Regarding Claim 14, Renard, as modified, describes the preparation method of claim 13.
Renard does not specifically describe wherein the plastic encapsulation preform is located between the light receiving unit and the substrate, and extends to the sidewalls of the light receiving unit and the driving chip.
Hu and Yap disclose, teach, or at least suggest the missing limitations. Hu discloses an encapsulation layer provided on the substrate to encapsulate and fix devices, and Yap discloses encapsulant flowing over and around embedded devices and a bonding layer positioned between stacked molded package layers (Hu, Paragraph 0075; Yap, Paragraphs 0022 and 0030 and Figures 2 and 6–7).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard to include wherein the plastic encapsulation preform is located between the light receiving unit and the substrate, and extends to the sidewalls of the light receiving unit and the driving chip, as disclosed, taught, or at least suggested by Hu and Yap.
It would have been obvious to combine and modify the cited references to position encapsulation material between the package elements and around the sidewalls of the devices to secure and encapsulate the devices within the molded package structure (Hu, Paragraph 0075; Yap, Paragraphs 0022 and 0030).
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Renard, in view of Hu, further in view of Lowenthal et al. U.S. P.G. Publication 2014/0151606 A1 (hereinafter, Lowenthal).
Regarding Claim 6, Renard, as modified, describes the packaging structure of claim 1.
Renard does not specifically describe wherein each of the first conductive layer and the second conductive layer comprises a conductive material, and the conductive material comprises a conductive ink or a conductive silver paste.
Lowenthal discloses, teaches, or at least suggests the missing limitations. Lowenthal discloses conductive ink compositions, including conductive ink containing silver particles, for forming conductive layers and traces (Lowenthal, Paragraphs 0254–0264).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard such that each of the first conductive layer and the second conductive layer comprises a conductive material, and the conductive material comprises a conductive ink or a conductive silver paste, as disclosed, taught, or at least suggested by Lowenthal.
It would have been obvious to combine and modify the cited references to form the conductive layers using conductive ink because the conductive ink is expressly disclosed for forming conductive electrical layers and traces (Lowenthal, Paragraphs 0254–0264).
Regarding Claim 18, Renard, as modified, describes the preparation method of claim 17.
Renard does not specifically describe wherein the conductive material comprises a conductive ink, solidify the conductive material comprises a first solidification stage and a second solidification stage after the first solidification stage; the first solidification stage comprises spraying the conductive ink onto the inner wall of each of the plurality of first channels and the inner wall of each of the plurality of second channels, and irradiating the conductive ink with ultraviolet light to pre-solidify the conductive ink; and the second solidification stage comprises baking the pre-solidified conductive ink to obtain the first conductive layer and the second conductive layer.
Hu and Lowenthal disclose, teach, or at least suggest the missing limitations. Hu discloses precisely spraying conductive paste or conductive metal paste into connection through holes along the inner walls, and Lowenthal discloses conductive ink that is first ultraviolet cured and subsequently thermally cured (Hu, Paragraph 0077 and Figures 4 and 9; Lowenthal, Paragraph 0264).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard such that the conductive material comprises a conductive ink, solidify the conductive material comprises a first solidification stage and a second solidification stage after the first solidification stage; the first solidification stage comprises spraying the conductive ink onto the inner wall of each of the plurality of first channels and the inner wall of each of the plurality of second channels, and irradiating the conductive ink with ultraviolet light to pre-solidify the conductive ink; and the second solidification stage comprises baking the pre-solidified conductive ink to obtain the first conductive layer and the second conductive layer, as disclosed, taught, or at least suggested by Hu and Lowenthal.
It would have been obvious to combine and modify the cited references to apply conductive ink along the inner walls of the channels and cure the conductive ink using ultraviolet curing followed by thermal curing because such application and sequential curing techniques are expressly disclosed for conductive materials (Hu, Paragraph 0077; Lowenthal, Paragraph 0264).
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Renard, in view of Hu, further in view of Dutta, and further in view of Oyama et al. U.S. P.G. Publication 2021/0156965A1 (hereinafter, Oyama).
Regarding Claim 7, Renard, as modified, describes the packaging structure of claim 2, wherein the first channel and the second channel are defined in the substrate (connection through holes 120a and 120b formed in substrate, Hu, Paragraphs 0069 and 0073 and Figures 4 and 9); …
Renard does not specifically describe the substrate further defines a first slot and a second slot, the light receiving unit is located on the second surface, the photosensitive area is exposed from the first slot, and each of the plurality of first hollow conductive channels extends through the substrate and toward the non-photosensitive area; the driving chip is located on the second surface, the light source is exposed from the second slot, and each of the plurality of second hollow conductive channels extends through the substrate and toward a top surface of the driving chip opposite to the first surface.
Oyama discloses, teaches, or at least suggests the missing limitations. Oyama discloses a circuit substrate positioned relative to a light emitting element and a light receiving element, with a first opening and a second opening formed in portions of the circuit substrate corresponding to the light emitting element and light receiving element, respectively, to permit light to pass through the substrate (Oyama, Paragraphs 0033-0035 and Figures 1-2). Dutta further discloses a driver chip having backside contacts connected through through-hole electrodes to an underlying optoelectronic substrate (Dutta, Paragraph 0121 and Figures 25A-25C).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard to include the substrate further defines a first slot and a second slot, the light receiving unit is located on the second surface, the photosensitive area is exposed from the first slot, and each of the plurality of first hollow conductive channels extends through the substrate and toward the non-photosensitive area; the driving chip is located on the second surface, the light source is exposed from the second slot, and each of the plurality of second hollow conductive channels extends through the substrate and toward a top surface of the driving chip opposite to the first surface, as disclosed, taught, or at least suggested by Hu, Dutta, and Oyama.
It would have been obvious to combine and modify the cited references to provide separate substrate openings corresponding to the light receiving element and light emitting element because the openings increase transmission of received and emitted light through the intervening substrate (Oyama, Paragraph 0035 and Figures 1–2).
Regarding Claim 16, Renard, as modified, describes the preparation method of claim 15.
Renard does not specifically describe wherein forming the light emitting unit and the light receiving unit on the substrate comprises: installing the light receiving unit and the driving chip on the second surface, wherein the photosensitive area is exposed from the first slot of the substrate, the light source is exposed from the second slot of the substrate, the second surface is also provided with a plastic encapsulation preform, the plastic encapsulation preform is at least adhered to the sidewalls of the light receiving unit and the driving chip, and partially located between the light receiving unit and the driving chip; and solidifying the plastic encapsulation preform to obtain the plastic encapsulation body.
Hu and Oyama disclose, teach, or at least suggest the missing limitations. Hu discloses providing and curing an encapsulation layer around devices mounted on the substrate, and Oyama discloses first and second substrate openings corresponding to the light emitting element and light receiving element, respectively (Hu, Paragraphs 0075 and 0082; Oyama, Paragraphs 0033-0035 and Figures 1-2).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the method of Renard to include wherein forming the light emitting unit and the light receiving unit on the substrate comprises: installing the light receiving unit and the driving chip on the second surface, wherein the photosensitive area is exposed from the first slot of the substrate, the light source is exposed from the second slot of the substrate, the second surface is also provided with a plastic encapsulation preform, the plastic encapsulation preform is at least adhered to the sidewalls of the light receiving unit and the driving chip, and partially located between the light receiving unit and the driving chip; and solidifying the plastic encapsulation preform to obtain the plastic encapsulation body, as disclosed, taught, or at least suggested by Hu and Oyama.
It would have been obvious to combine and modify the cited references to encapsulate the devices on the substrate while exposing the light receiving and light emitting elements through corresponding substrate openings because the encapsulation protects and fixes the devices while the openings permit received and emitted light to pass through the substrate (Hu, Paragraphs 0075 and 0082; Oyama, Paragraph 0035 and Figures 1-2).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Renard, in view of Hu, further in view of Pohl et al. U.S. P.G. Publication 2009/0008793A1 (hereinafter, Pohl).
Regarding Claim 9, Renard, as modified, describes the packaging structure of claim 1.
Renard does not specifically describe wherein a thickness of the first conductive layer is greater than or equal to 500 nm.
Pohl discloses, teaches, or at least suggests the missing limitation. Pohl discloses through holes lined with an electrically conductive layer having a thickness between 0.2 μm and 75 μm, and particularly between 1 μm and 10 μm (Pohl, Paragraph 0022 and Figures 8A-8C).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard such that a thickness of the first conductive layer is greater than or equal to 500 nm, as disclosed, taught, or at least suggested by Pohl.
It would have been obvious to combine and modify the cited references to use a conductive layer having a thickness greater than or equal to 500 nm because the disclosed conductive-layer range includes thicknesses greater than the claimed 500 nm for circuit design (Pohl, Paragraph 0022 and Figures 8A-8C).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Renard, in view of Hu, further in view of Luan U.S. P.G. Publication 2013/0320471A1 (hereinafter, Luan).
Regarding Claim 20, Renard describes a packaging structure comprising:
-a substrate module comprising a substrate (substrate, Renard, Paragraphs 0015-0016 and Figures 1A-1D); …
-and a light emitting unit and a light receiving unit located on the substrate (light-emitting device and image sensor die located on substrate, Renard, Paragraphs 0015, 0017, and 0020 and Figures 1A-1D), the light receiving unit comprising a photosensitive area and a non-photosensitive area connected to the photosensitive area (image sensor 22 and active surface including electrical circuitry of image sensor die 14, Renard, Paragraphs 0018 and 0026 and Figures 1A-1D); …
Renard does not specifically describe the substrate module defining a plurality of first hollow conductive channels and a plurality of second hollow conductive channels; wherein each of the plurality of first hollow conductive channels comprises a first channel and a first conductive layer formed on an inner wall of the first channel, two ends of the first channel extend to the substrate and the non-photosensitive area, respectively, each of the plurality of first hollow conductive channels is electrically connected to the substrate and the non-photosensitive area; each of the plurality of second hollow conductive channels comprises a second channel and a second conductive layer formed on an inner wall of the second channel, two ends of the second channel extend to the substrate and the light emitting unit, respectively, the plurality of second hollow conductive channels is electrically connected to the substrate and the light emitting unit.
Hu discloses, teaches, or at least suggests the missing limitations. Hu discloses connection through holes extending between substrate circuitry and respective device pins, with conductive material bonded to the inner walls of the connection through holes and respective device pins to form conductive layers electrically connecting the devices to the substrate (Hu, Paragraphs 0073 and 0076-0077 and Figures 4 and 9).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of
Renard to include the substrate module defining a plurality of first hollow conductive channels and a plurality of second hollow conductive channels; wherein each of the plurality of first hollow conductive channels comprises a first channel and a first conductive layer formed on an inner wall of the first channel, two ends of the first channel extend to the substrate and the non-photosensitive area, respectively, each of the plurality of first hollow conductive channels is electrically connected to the substrate and the non-photosensitive area; each of the plurality of second hollow conductive channels comprises a second channel and a second conductive layer formed on an inner wall of the second channel, two ends of the second channel extend to the substrate and the light emitting unit, respectively, the plurality of second hollow conductive channels is electrically connected to the substrate and the light emitting unit, as disclosed, taught, or at least suggested by Hu.
It would have been obvious to combine and modify the cited references to electrically connect the devices to the substrate using conductive layers formed along inner walls of connection through holes because such connections reduce the overall package volume while providing stable electrical connections between the devices and substrate circuitry (Hu, Paragraphs 0030-0031).
Renard further does not specifically describe a camera module comprising: a lens assembly; and the lens assembly is located on the substrate module.
Luan discloses, teaches, or at least suggests the missing limitations. Luan discloses a camera module including an optical sensor package and a lens assembly aligned with and coupled to the optical sensor package (Luan, Paragraphs 0042-0050 and Figures 12-14).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the packaging structure of Renard to include a camera module comprising: a lens assembly; and the lens assembly is located on the substrate module, as disclosed, taught, or at least suggested by Luan.
It would have been obvious to combine and modify the cited references to provide a lens assembly on the optical sensor package because the lens assembly provides a low-profile camera module while controlling the positioning and spacing of the lens assembly relative to the optical sensor package (Luan, Paragraphs 0042-0047 and Figures 12-13).
Conclusion
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/ANDREW J CROMER/Examiner, Art Unit 3667
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