DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Response to Arguments
Applicant’s arguments filed 02 July 2026, with respect to the rejection(s) of claim(s) 1, 11, and 17 under 35 U.S.C. 103(a) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the newly cited prior art presented below.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 is amended to recite the term “solid state-storage drives” in lines 2 and 4 of the claim, which appears to reference the same element as the “solid-state storage drives” recited throughout the rest of the claims. The Examiner requests Applicant amend the limitations to use consistent terminology throughout the claims, specifically the location of the hyphen between “solid” and “state” or between “state” and “storage.”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 12, 14 – 18, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 8, 10, 11, and 13 – 16 of U.S. Patent No. 12,210,476 in view of US Patent No. 10,86,213 (hereinafter Singh).
Claims 1, 10, and 15 of U.S. Patent No. 12,210,476 requires all the limitations of claims 1, 11, and 17 of the instant application, respectively, except the limitation of “wherein a processor in a first node is configurable to access a solid-state storage drive in a second storage node through the switch without routing communications through a processor of the second storage node.”
However, Singh teaches a storage system in which a processor (Singh; Figure 4 “CPU,” Figure 7 “CPU”) in a first storage node (Singh; Figure 1 Items 102, Figure 7 Items 102) is configurable to access a solid-state storage (Singh; Figure 4 Item 404, Figure 7 Items 302, Col 20 Lines 56 – 59) drive in a second storage node through the switch (Singh; Figure 4 Item 402, Figure 7 Item 402) without routing communications through a processor of the second storage node (Singh; Col 19 Lines 22 – 33).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the claims of U.S. Patent No. 12,210,476 to include the teachings of Singh because doing so allows for high performance and low latency (Singh; Col 19 Lines 30 – 31).
Additionally, the claims of the instant application are mapped to the claims of U.S. Patent No. 12,210,476 as shown in the table below:
Instant App
12,210,476
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
3
10
1
11
10
12
11
14
13
15
14
16
10
17
15
18
16
20
15
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 3, 6 – 13, and 16 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,860,213 (hereinafter Singh) in view of US Patent No. 9,565,269 (hereinafter Malwankar).
As per claim 1, Singh teaches a storage cluster comprising: a plurality of storage nodes (Singh; Figure 1 Items 102, Figure 7 Items 102) comprising solid-state storage drives coupled together (Singh; Figure 4 Item 404, Figure 7 Items 302, Col 20 Lines 56 – 59); and a switch (Singh; Figure 4 Item 402, Figure 7 Item 402) that direct network-connects a plurality of processors (Singh; Figure 4 “CPU,” Figure 7 “CPU”), as compute resources in the plurality of storage nodes (Singh; Col 20 Lines 3 – 39), and the solid-state storage drives of the plurality of storage nodes, wherein a processor in a first storage node (Singh; Figure 4 “CPU,” Figure 7 “CPU”) is configurable to access a solid-state storage drive in a second storage node through the switch without routing communications through a processor of the second storage node (Singh; Col 19 Lines 22 – 33).
Singh does not explicitly teach the solid-state storage drives including a controller.
However, Malwankar teaches a storage node in a storage system including solid-state storage drives which each include a controller (Malwankar; Col 5 Lines 29 – 31).
Therefore, it would have neem obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Singh to include the SSD controllers because doing so allows for properly performing memory operations on the SSD.
As per claim 2, Singh also teaches wherein the plurality of storage nodes comprises a homogeneous set of hybrid compute and storage nodes (Singh; Col 8 Lines 47 – 60).
As per claim 3, Singh also teaches wherein the plurality of storage nodes comprises a heterogeneous mix of compute-only nodes, storage-only nodes or hybrid compute and storage nodes (Singh; Col 8 Lines 47 – 60).
As per claim 6, Singh in combination Malwankar also teaches the plurality of storage nodes configurable to have Ethernet communication among the plurality of processors and the solid-state storage drives (Singh; Figure 7 Item 402), through the switch and direct network connection to each of the plurality of processors and the solid-state storage drives, without PCIe (peripheral component interconnect express) (Malwankar; Col 3 Lines 36 – 61, Col 5 Lines 1 – 28).
As per claim 7, Singh also teaches wherein the plurality of nodes are internally and externally connected through a PCIe (peripheral component interconnect express) connection (Singh; Col 23 Lines 26 – 30).
As per claim 8, Singh also teaches wherein at least one of the storage nodes having solid-state storage drives therein comprises: flash memory (Singh; Col 20 Lines 54 – 59); and a NIC (Singh; Figure 5 Item 118, Figure 8 Item 854, Figure 9 Items 908 and 118) connected to the flash memory and direct-network connected to the switch.
As per claim 9, Singh also teaches wherein at least one of the storage nodes having solid-state storage drives therein comprises: flash memory (Singh; Col 20 Lines 54 – 59); and a flash memory controller (Singh; Figure 5 Item 300, Figure 7 Item 300, Figure 8 Item 800) connected to the flash memory and direct-network connected to the switch.
As per claims 10 and 16, Singh also teaches wherein the plurality of storage nodes has independent local compute resources (Singh; Figure 4 “CPU,” Figure 7 “CPU”) and independent local storage resources (Singh; Figure 7 Items 308 and 310) and the at least one of the plurality of storage nodes has a first connection through which the independent local compute resources can access the independent local storage resources (Singh; Figure 8 Item 802), and a second connection through which the compute resources on further storage nodes can access the independent local storage resources of the at least one of the plurality of storage nodes (Singh; Figure 8 Items 854).
As per claim 11, Singh teaches a storage system comprising: a plurality of storage nodes (Singh; Figure 1 Items 102, Figure 7 Items 102) having solid-state storage drives (Singh; Figure 4 Item 404, Figure 7 Items 302, Col 20 Lines 56 – 59); and a switch (Singh; Figure 4 Item 402, Figure 7 Item 402) coupled to the plurality of storage nodes, the switch providing a direct network-connection between a plurality of processors (Singh; Figure 4 “CPU,” Figure 7 “CPU”), as compute resources in the plurality of storage nodes (Singh; Col 20 Lines 3 – 39) such that compute resources and the solid-state storage drives are disaggregated in the storage system, wherein processors in remote storage nodes (Singh; Figure 4 “CPU,” Figure 7 “CPU”) access the solid-state storage drives through the switch without utilizing compute resources local to the storage node containing the solid-state storage drives (Singh; Col 19 Lines 22 – 33).
Singh does not explicitly teach the solid-state storage drives including a controller.
However, Malwankar teaches a storage node in a storage system including solid-state storage drives which each include a controller (Malwankar; Col 5 Lines 29 – 31).
Therefore, it would have neem obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Singh to include the SSD controllers because doing so allows for properly performing memory operations on the SSD.
As per claim 12, Singh also teaches wherein the plurality of storage nodes comprises a homogeneous set of hybrid compute and storage nodes (Singh; Col 8 Lines 47 – 60) or a heterogeneous mix of compute-only nodes having one or more processors and no solid-state storage drives, storage-only blades each having solid-state storage drives or hybrid compute and storage nodes each having one or more processors and solid-state storage drives (Singh; Col 8 Lines 47 – 60).
As per claims 13 and 19, Singh also teaches wherein each of the plurality of processors communicates with each of the solid-state storage drives in the plurality of storage nodes through the switch, using Ethernet protocol (Singh; Col 19 Lines 22 – 33).
As per claim 17, Singh teaches a method comprising, communicating from a processor (Singh; Figure 4 “CPU,” Figure 7 “CPU”) in a first storage node of a plurality of storage nodes (Singh; Figure 1 Items 102, Figure 7 Items 102), through a switch (Singh; Figure 4 Item 402, Figure 7 Item 402), directly to a solid-state storage drive (Singh; Figure 4 Item 404, Figure 7 Items 302, Col 20 Lines 56 – 59) in a second storage node of the plurality of storage nodes, without routing communications through a processor in the second storage node (Singh; Col 19 Lines 22 – 33), wherein the switch direct network-connects a plurality of processors as compute resources in the plurality of storage nodes to solid-state storage drives in the plurality of storage nodes (Singh; Col 19 Lines 22 – 33), and wherein at least one of the plurality of storage nodes, distinct from the first and second storage nodes, has independent local compute resources (Singh; Figure 4 “CPU,” Figure 7 “CPU”) and independent local storage resources (Singh; Figure 7 Items 308 and 310); and communicating from a solid-state storage drive in a third storage node, through the switch, to a processor in a fourth blade of the storage system (Singh; Col 19 Lines 22 – 33 – Singh teaches that there can be more than just the two computing systems illustrated in Figure 4).
Singh does not explicitly teach the solid-state storage drives including a controller.
However, Malwankar teaches a storage node in a storage system including solid-state storage drives which each include a controller (Malwankar; Col 5 Lines 29 – 31).
Therefore, it would have neem obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Singh to include the SSD controllers because doing so allows for properly performing memory operations on the SSD.
As per claim 18, Singh also teaches wherein the communicating from the processor in the first storage node, through the switch, to the solid-state storage drive in the second storage node comprises one of communicating to Ethernet-connectable flash memory in the second storage node or communicating through a NIC (network interface card or network interface controller) (Singh; Figure 5 Item 118, Figure 8 Item 854, Figure 9 Items 908 and 118) to flash memory in the second storage node.
As per claim 20, Singh also teaches wherein at least one of the plurality of storage nodes has a first connection through which the independent local compute resources can access the independent local storage resources (Singh; Figure 8 Item 802), and a second connection through which the compute resources on further storage nodes can access the independent local storage resources of the at least one of the plurality of storage nodes (Singh; Figure 8 Items 854).
Claim(s) 4 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,860,213 (hereinafter Singh) in view of US Patent No. 9,565,269 (hereinafter Malwankar), and further in view of US Patent No. 9,003,144 (hereinafter Hayes).
As per claims 4 and 15, Singh in combination with Malwankar teaches the invention as described per claims 1 and 11 (see rejections of claims 1 and 11 above).
Singh in combination with Malwankar does not teach wherein the at least one of the plurality of storage nodes includes a plurality of authorities, each of the plurality of authorities controlling where data owned by respective authority is stored.
However, Hayes teaches a storage system in which storage nodes include a plurality of authorities (Hayes; Figure 4 Item 168) controlling where data owned by the authority is stored (Hayes; Col 6 Lines 44 – 53).
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to have modified the teachings of Singh in combination with Malwankar to include the authorities because doing so allows for assisting in determining the type of erasure encoding scheme to apply to data and which storage nodes have which portions of data (Hayes; Col 6 Lines 44 – 53).
Allowable Subject Matter
Claims 5 and 14 would be allowable if rewritten, amended, or a terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 5 would be allowable if rewritten, amended, or a terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination a processor of the plurality of processors assignable to a storage node independent of whether the assigned storage node has a corresponding solid-state storage drive that is controlled by the processor, as required by dependent claim 5, in combination with the other claimed limitations (emphasis added). The prior art of record teaches a distributed computing and storage system (Singh; Figure 7) which allows processors of a storage node direct access to storage of another storage node, but does not teach assigning a processor to a storage node independent of whether the storage node has a corresponding solid-state storage drive that is controlled by the processor, as required by dependent claim 5.
Claim 14 would be allowable if rewritten, amended, or a terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination wherein each of the plurality of storage nodes that has one or more of the plurality of processors selectable to function as a controller for one of the solid-state storage drives without requiring the processor to be on a same storage node as the one of the solid-state storage drives, as required by dependent claim 15, in combination with the other claimed limitations (emphasis added). The prior art of record teaches a distributed computing and storage system (Singh; Figure 7) which allows processors of a storage node direct access to storage of another storage node, but does not teach assigning a processor to a storage node independent of whether the storage node is on the same storage node as the solid-state storage drive, as required by dependent claim 14.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181
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