DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/10/2025 and 2/19/2025 were considered by the examiner.
Drawings
The drawings received on 1/10/25 have been accepted by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jayasena et al. [US 2014/0181427], Applicant Cited Art, in view of Moreau et al. [“A Hardware Software Blueprint for Flexible Deep Learning Specialization”].
Claim 1, Jayasena et al. discloses a system comprising: at least one memory unit [Fig 1 and Abstract]; and at least one processor comprising one or more processor cores [par. 0004-0005], wherein the at least one processor is configured to access the at least one memory unit using an instruction set [par. 0007] comprising a tensor of the at least one memory unit to be accessed, the tensor having at least two dimensions [par. 0030]. Jayasena et al. does not teach by Moreau et al. discloses the instruction set further comprising a submatrix memory command associated with the tensor [see Abstract]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Jayasena et al. to include the submatrix memory command associated with a tensor as disclosed by Moreau et al. since doing so minimizes memory bandwidth bottlenecks and reduces CPU instruction overhead.
Claim 2, Jayasena et al. in view of Moreau et al. discloses the system of claim 1, wherein the instruction set comprises a length associated with the tensor [par. 0030].
Claim 3, Jayasena et al. in view of Moreau et al. discloses the system of claim 1, wherein the tensor has at least three dimensions [par. 0030].
Claim 4, Jayasena et al. in view of Moreau et al. discloses the system of claim 1, wherein the tensor has at least four dimensions [par. 0030].
Claim 5, Jayasena et al. in view of Moreau et al. discloses the system of claim 1, wherein the instruction set includes a pointer associated with a memory address [start address and element count, par. 0025].
Claim 6, Jayasena et al. in view of Moreau et al. discloses the system of claim 1, wherein the at least one memory unit comprises random-access memory [par. 0005 and 0081].
Claim 8, Jayasena et al. in view of Moreau et al. discloses the system of claim 1, further comprising at least one buffer configured to store data retrieved from the memory unit [par. 0023].
Claim 9, Jayasena et al. in view of Moreau et al. discloses the system of claim 1, wherein the instruction set is configured to be executed according to an instruction pipeline [sequence of memory accesses constitutes a pipeline, par. 0023].
Claim 10, Jayasena et al. in view of Moreau et al. discloses the system of claim 1, wherein the one or more processor cores comprise multiple independent processor cores [multiple processors disclosed, par. 0004-0005].
Claims 11-16 and 18-20 are rejected using the same rationale as claims 1-6 and 8-10 above.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Jayasena et al. [US 2014/0181427], Applicant Cited Art, in view of in view of Moreau et al. [“A Hardware Software Blueprint for Flexible Deep Learning Specialization”], further in view of Jewett et al. [US 2002/0049825], Applicant Cited Art.
Claim 7, Jayasena et al. in view of in view of Moreau et al. discloses the system of claim 1, further comprising conductive lines coupling the at least one memory unit and the at least one processor [memory bus, par. 0071]. Jayasena et al. in view of in view of Moreau et al. does not teach but Jewett et al. discloses the conductive lines provide a sixty four-bit width [par. 0040]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the tensor based memory access system using a 64 bit memory bus since doing so increases bandwidth and reduces latency.
Claim 17 is rejected using the same rationale as claim 7.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MIDYS ROJAS/Primary Examiner, Art Unit 2133
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