DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to communications dated 3/20/2025.
Claims 1-21 are pending.
Claims 1-21 are rejected.
Information Disclosure Statement
The information disclosure statements (IDSes) submitted on 1/10/2025 and 11/10/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 11-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Exemplary independent claim 1 recites “…a processor core; a memory configured to store a set of data; a memory control circuit coupled between the processor core and the memory; and a set of registers that includes fields configured to store a set of parameters that define the set of data using a set of nested loops that includes a first lop and a second loop, wherein the fields include: a first field configured to store a first block size value; a second field configured to store a second block size value; a third field configured to store a value that specifies whether to determine a first block size associated with the first loop based on the first block size value and independent of the second block size value or based on both the first block size value and the second block size value; and a fourth field configured to store a value that specifies whether to determine a second block size associated with the second loop based on the first block size value and independent of the second block size value or based on both the first block size value and the second block size value; wherein the memory control circuit is configured to: retrieve the set of data using the set of parameters; and provide the set of data to the processor core” (exemplary independent claim 1, lines 2-20).
The Examiner is uncertain if the recitation of “…a third field configured to store a value that specifies whether to determine a first block size associated with the first loop based on the first block size value and independent of the second block size value or based on both the first block size value and the second block size value…” means any of the following:
“a third field” that is “configured to store a value that specifies whether to determine a first block size associated with the first loop” determines “a value” “based on the first block size value” that is “independent of the second block size value” (i.e., different from “the second block size value”) or “a value” is determined “based on both the first block size value and the second block size value”;
“a third field” that is “configured to store a value that specifies whether to determine a first block size associated with the first loop” determines “a value” “based on the first block size value” such that “a value” is determined “independent of the second block size value” (i.e., without using “the second block size value”) or “a value” is determined “based on both the first block size value and the second block size value”; or
some other possible, unconsidered interpretation.
Similarly, the Examiner is uncertain if the recitation of “…a fourth field configured to store a value that specifies whether to determine a second block size associated with the second loop based on the first block size value and independent of the second block size value or based on both the first block size value and the second block size value…” means any of the following:
“a fourth field” that is “configured to store a value that specifies whether to determine a second block size associated with the second loop” determines “a value” “based on the first block size value” that is “independent of the second block size value” (i.e., different from “the second block size value”) or “a value” is determined “based on both the first block size value and the second block size value”;
“a fourth field” that is “configured to store a value that specifies whether to determine a second block size associated with the second loop” determines “a value” “based on the first block size value” such that “a value” is determined “independent of the second block size value” (i.e., without using “the second block size value”) or “a value” is determined “based on both the first block size value and the second block size value”; or
some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…a processor core; a memory configured to store a set of data; a memory control circuit coupled between the processor core and the memory; and a set of registers that includes fields configured to store a set of parameters that define the set of data using a set of nested loops that includes a first lop and a second loop, wherein the fields include: a first field configured to store a first block size value; a second field configured to store a second block size value; a third field configured to store a value that specifies whether to determine a first block size associated with the first loop based on the first block size value and independent of the second block size value or based on both the first block size value and the second block size value; and a fourth field configured to store a value that specifies whether to determine a second block size associated with the second loop based on the first block size value and independent of the second block size value or based on both the first block size value and the second block size value; wherein the memory control circuit is configured to: retrieve the set of data using the set of parameters; and provide the set of data to the processor core” to read “…a processor core; a memory configured to store a set of data; a memory control circuit coupled between the processor core and the memory; and a set of registers that includes fields configured to store a set of parameters that define the set of data using a set of nested loops that includes a first loop and a second loop, wherein the fields include: a first field configured to store a first block size value; a second field configured to store a second block size value; a third field configured to store a value that specifies whether to determine a first block size associated with the first loop based on either of the first block size value without using the second block size value or based on both the first block size value and the second block size value; and a fourth field configured to store a value that specifies whether to determine a second block size associated with the second loop based on the first block size value and independent of the second block size value or based on both the first block size value and the second block size value; wherein the memory control circuit is configured to: retrieve the set of data using the set of parameters; and provide the set of data to the processor core.”
Dependent claims 2-10, which ultimately depend from exemplary independent claim 1, are rejected for carrying the same deficiencies.
The Examiner notes that independent claim 11 recites similar unclear clauses about “a first value” and “a second value” as those explained above with respect to exemplary independent claim 1. Independent claim 11 is therefore rejected for carrying the same deficiencies, mutatis mutandis, as given above with respect to exemplary independent claim 1. For the sake of examination, independent claim 11 is being interpreted similarly to the above interpretation of exemplary independent claim 1, mutatis mutandis.
Dependent claims 12-21, which ultimately depend from independent claim 11, are rejected for carrying the same deficiencies.
Conclusion
The following prior art is made of record and is not relied upon for any rejection but is considered pertinent to Applicant's disclosure:
U.S. Patent No. 6,941,447: teaches a superscalar processor that uses a stream register with out-of-order execution of instructions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135
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