Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 8 is objected to because of the following informalities:
The phrase “determination that the first redundancy memory cell row available” is missing the word ‘is’.
Claim 19 is objected to because of the following informalities:
The phrase “a plurality of memory dies stacked one another” is missing a preposition.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 4, 10 – 12 and 16 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by O’Connell (US Patent Application Publication 2013/0215695).
Regarding claim 1, O’Connell teaches a semiconductor device (Paragraph 0023, the device contains at least the semiconductor of the eDRAM) comprising:
a host (Fig. 1, the ASIC 130; Paragraph 0022, the failed address engine determines the type of failure and action to be taken; Paragraph 0014, the rest of the SoC that is not shown); and
a memory device (Fig. 1, eDRAM 120-1-1) comprising a first memory cell array corresponding to a plurality of word lines (Fig. 3, the memory array 410) and a second memory cell array corresponding to a plurality of redundancy word lines (Fig. 3, the redundancy memory 420),
wherein the host is configured to (Paragraph 0037, the self-repair engine may be part of the failed address engine on the ASIC. Furthermore O’Connell is not limited by the location of the self-repair engine), based on an occurrence of a first type of error that is correctable through an error correction code (ECC) in a first memory cell row connected to a first word line in the first memory cell array, correct the first type of error through the error correction code (Paragraphs 0038 – 0043, a soft error is detected and resolved based on the ECC. In the example provided in paragraphs 0041 and 0042, the error occurs in row 415, which is in the first memory cell array), and
wherein the host is configured to, based on a number of the occurrence of the first type of error in the first memory cell row exceeding a predetermined threshold value (Paragraph 0022, a soft error occurring a second or third time is an indication of a hard error), deactivate the first word line and activate a first redundancy word line corresponding to the first word line among the plurality of redundancy word lines (Paragraph 0022, in that case, the failed address engine has the redundancy engine repair the failed address using spare redundancy).
Regarding claim 2, O’Connell teaches the semiconductor device of claim 1, wherein the host comprises:
a controller configured to control an operation of the memory device (Paragraph 0023, the circuits outside the DRAM can control the operation of the memory device via signals; Paragraph 0024, the ECC engine sends signals);
a physical layer connected between the controller and the memory device (Fig. 2, the pins in and out of the eDRAM), the physical layer being configured to transmit and receive a repair command (Paragraph 0024, the SR_FLAG and ECC_FLAG signals), a data command (Paragraph 0024, the read and write commands), an address (Paragraph 0024, the ADDR signal) and data to and from the memory device (Paragraph 0024, the DIN and DOUT signals) through a command/address channel (Fig. 2, the PADDR, PDIN, PCMD and PDOUT pins).
Regarding claim 3, O’Connell teaches the semiconductor device of claim 2, wherein the controller is configured to, based on the number of the occurrence of the first type of error in the first memory cell row exceeding the predetermined threshold value (Paragraph 0046, the occurrence of a second error indicating a hard error), determine whether the first memory cell row is in an idle state (Paragraphs 0025 and 0048, in some embodiments, when the eDRAM recognizes there is a hard error, it waits to perform the self-repair until it receives a NOP operation. The NOP operation is one where there is no conflicting operation to the memory areas, that is, the memory areas are in an idle state), and
wherein the controller is configured to, based on a determination that the first memory cell row is in the idle state, deactivate the first word line and activate the first redundancy word line (Paragraph 0025, the self-repair; Paragraph 0052, the self-repair redirects access to the failed word to the redundant word).
Regarding claim 4, O’Connell teaches the semiconductor device of claim 3, wherein the controller is configured to, based on a determination that the first memory cell row is not in the idle state, block a first data command from being applied to the first memory cell row to allow the first memory cell row to transition to the idle state (Paragraph 0024, the SR_FLAG is raised to request a NOP instruction. CMD is a single signal used to receive the read/write data commands and the NOP instruction. Paragraph 0048, the engine will wait until the occurrence of a NOP instruction. If the memory is not in the idle state, it will not repair until the memory transitions to an idle state through the NOP instruction. The repair occurs “in” the NOP instruction, while NOP occupies the CMD signal. That is, other read/write data commands are blocked for the duration of the NOP to allow the memory areas to transition into the idle state).
Regarding claim 10, O’Connell teaches the semiconductor device of claim 1, wherein the memory device comprises a plurality of memory dies (Paragraph 0023, the eDRAM is a physical semiconductor chip; Paragraphs 0016, 0026 – 0031, the memory is composed of a plurality of hardware blocks/circuits).
Regarding claim 11, O’Connell teaches a method of repairing a memory device, comprising:
detecting an occurrence of an error in a first memory cell row connected to a first word line of a first memory cell array included in the memory device (Paragraph 0041/0042, an erroneous bit in the memory is detected. Paragraph 0041 indicates it may occur a first memory cell row connected to a first word line of a first memory cell array);
correcting, based on the detected error being of a first type that is correctable through an error correction code (ECC), the first type of error through the error correction code (Paragraph 0043/0044, if the error is a soft error, the erroneous bit is corrected, then marked by the ECC engine);
deactivating the first word line and activating a first redundancy word line corresponding to the first word line, based on a number of an occurrence of the first type of error in the first memory cell row exceeding a predetermined threshold value (Paragraph 0022, a soft error occurring a second or third time is an indication of a hard error, which is repaired by a redundancy word line replacing the failed word line).
Claim 12 recites similar language to claims 3 and 4, and is similarly rejected.
Claim 16 recites similar language to claim 1, and is similarly rejected.
Regarding claim 17, O’Connell teaches the semiconductor device of claim 16, wherein the host is configured to, based on the detected error being of the first type, correct the first type of error in the first memory cell using the error correction code (Paragraphs 0038 – 0043, a soft error is detected and resolved based on the ECC).
Claim 18 recites similar language to claims 3 and 4, and is similarly rejected.
Claim 19 recites similar language to claims 2 and 10, and is similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over O’Connell in view of the Authoritative Dictionary of IEEE Standards Terms (NPL), hereinafter the IEEE dictionary
Regarding claim 5, O’Connell teaches the semiconductor device of claim 2, wherein the host further comprises a central processing unit (Paragraph 0014), and the controller is configured to, based on the number of the occurrence of the first type of error in the first memory cell row exceeding the predetermined threshold value, deactivate the first word line and activate the first redundancy word line in response to a self-refresh command (Paragraph 0048, the repair in response to the NOP command).
O’Connell does not explicitly teach that the self-refresh command is provided from the central processing unit.
O’Connell does, however, teach that the NOP commands are commonly available in an application using the DRAM (Paragraph 0060).
The IEEE Dictionary entry for central processing unit teaches that the CPU fetches, decodes, and executes programmed instructions (Page 155).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the NOP instructions of O’Connell would be provided from the central processing unit. It would be obvious because that is the well-known and conventional function of a CPU as taught by the IEEE Dictionary. Given that O’Connell teaches that applications (i.e. programmed instructions) commonly include NOP instructions, it would be clear to one of ordinary skill in the art that the applications taught by O’Connell are run on the CPU, making the NOP instructions self-refresh commands provided from the CPU.
Claim 13 recites similar language to claim 5, and is similarly rejected.
Claim 20 recites similar language to claim 5, and is similarly rejected.
Claims 6, 7, 8, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over O’Connell in view of Kurkowski (US Patent 5235548).
Regarding claim 6, O’Connell teaches the semiconductor device of claim 2, wherein the controller is configured to block the first word line (Paragraph 0032, attempted access to the erroneous memory is redirected) based on an occurrence of a second type of error that is uncorrectable through the ECC in the first memory cell (Paragraph 0027 and 0044, hard errors persist through attempting to correct them through the ECC).
O’Connell does not explicitly teach to cut off a power supplied to the memory device.
Kurkowski teaches to cut off a power supplied to the memory device when a row is defective in a memory with redundant rows (Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to, in the device of O’Connell, cut off a power supplied to the memory device, as taught by Kurkowski. One would be motivated to do so as it provides the benefits of higher power efficiency (Kurkowski column 1 line 59 – Column 2 line 20). It would be clear to one of ordinary skill in the art that, if it is known a row has a permanent error, it would not be necessary to continue providing it power after it has been replaced.
Regarding claim 7, O’Connell in view of Kurkowski teaches the semiconductor device of claim 6, wherein the controller is configured to, based on the occurrence of the second type of error in the first memory cell row, deactivate the first word line and activate the first redundancy word line, and block the first word line (O’Connell paragraph 0052, redirecting the failed word line to the redundant one) based on data written in a first redundancy memory cell row connected to the first redundancy word line of the second memory cell array being equal to data read from the first redundancy memory cell row (O’Connell paragraph 0032 teaches that the redundant memory can have its failures detected and repaired in a similar manner to the first memory, and that another redundant row will replace a failed redundant row. O’Connell paragraphs 0039 – 0042 teach that errors are detected when the data written does not match the data read. Given that another redundant row would be provided to replace a failed redundant row, the redundant row that replaces the original failed row will be one which does not contain an error, where data written is equal to data read).
Regarding claim 8, O’Connell in view of Kurkowski teaches the semiconductor device of claim 7, wherein the controller is configured to, based on the occurrence of the second type of error in the first memory cell row, determine whether the first redundancy memory cell row corresponding to the first memory cell row is available in the second memory cell array and activate the first redundancy word line connected to the first redundancy memory cell row based on a determination that the first redundancy memory cell is available (O’Connell paragraph 0032, it is determined whether there are remaining redundancy rows that can recover hard errors based on the full signal).
Claim 14 recites similar language to claim 7, and is similarly rejected.
Claims 9 and 15 rejected under 35 U.S.C. 103 as being unpatentable over O’Connell in view of the IEEE Dictionary as applied to claim 5 above, and further in view of another entry of the IEEE Dictionary and Kim (US Patent Application Publication 2008/0162814).
Regarding claim 9, O’Connell in view of the IEEE Dictionary as applied to claim 5 teaches the semiconductor device of claim 5.
O’Connell in view of the IEEE Dictionary as applied to claim 5 does not explicitly teach that the controller is configured to, in a state in which the first word line is deactivated and the first redundancy word line is activated, block the first word line in response to a shutdown command provided from the central processing unit and cut off a power supplied to the memory device (O’Connell does not describe a shutdown command).
The IEEE Dictionary teaches that a shutdown cuts off a power supplied to the memory device, and teaches that commonly known circuitry exists that is used to block memory during power on or power off (Page 542, inadvertent write protection).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention that the device of O’Connell in view of the IEEE Dictionary as applied to claim 5 would cut off a power supplied to the memory device as part of a shutdown, as taught by the IEEE Dictionary. It would further be obvious that the word line would be blocked by inadvertent write protection as part of the shutdown as taught by the IEEE dictionary. One would be motivated to do so because these are all well-known and conventional functions of a computer as taught by a dictionary, and because blocking the memory would prevent changes to the memory in an uncontrolled state (IEEE Dictionary inadvertent write protection).
Kim teaches a shutdown command sent by the CPU (Paragraph 0038).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that shutting down the memory would be in response to a shutdown command from the CPU. It would be obvious because the CPU may describe the majority of the computer system and/or is responsible for execution instructions, making it a clear choice for a source of any command (IEEE Dictionary central processing unit), and because it allows for the CPU to perform necessary operations on the memory before shutting it down (Kim paragraph 0038). One of ordinary skill in the art would recognize that, because shutting down the memory places it in an uncontrolled state (IEEE Dictionary inadvertent write protection), it would be advantageous to control when it enters that uncontrolled state.
Claim 15 recites similar language to claim 9, and is similarly rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bower et al. (US Patent Application Publication 2006/0101303) and Healy et al. (US Patent Application Publication 2016/0224412) teach systems using thresholds to determine whether an error that cannot be corrected by ECC occurs, and performing repair operations in response. Wilson (US Patent Application Publication 2020/0117558) teaches a method which tests the functionality of the redundant row.
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/B.P.H./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114