Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Claim Objections, filed April 29, 2026, with respect to the objections to claims 8 and 19 have been fully considered and are persuasive. The objections to the claims have been withdrawn.
Applicant’s arguments, see Claim Rejections – 35 U.S.C. § 102 & § 103, filed April 29, 2026, with respect to rejections of claims 1 – 4, 6 – 12, and 14 – 19 have been fully considered and are persuasive. The inclusion of additional limitations in the claims has narrowed the scope of the claims to the self-refresh behavior of the system, rather than the broader mapping applied to the previous rejection. The rejection of the claims has been withdrawn. However, a new rejection is made in new of art found in a search of the prior art prompted by amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 9 – 12, and 15 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ware et al. (US Patent Application Publication 2014/0351673), hereinafter Ware in view of Utsumi (US Patent Application Publication 2009/0235271).
Regarding claim 1, Ware teaches a semiconductor device (Paragraph 0068) comprising:
a host comprising a controller configured to control an operation of a memory device (Paragraph 0021, memory controller 104); and
the memory device comprising a first memory cell array corresponding to a plurality of word lines (Paragraph 0025, the bank with rows and columns) and a second memory cell array corresponding to a plurality of redundancy word lines (Paragraph 0032, a mat of spare sub-rows),
wherein the host is configured to, based on an occurrence of a first type of error that is correctable through an error correction code (ECC) (Paragraph 0024) in a first memory cell row connected to a first word line in the first memory cell array, correct the first type of error through the error correction code (Paragraph 0036, the system may be configured such that if the error is minor/single-bit, the error is corrected via the error detection and correction code), and
wherein the host is configured to, based on a number of the occurrence of the first type of error in the first memory cell exceeding a predetermined threshold value, deactivate the first word line and activate a first redundancy word line (Paragraph 0052, using a spare storage location based on the threshold number of detected errors exceeding the EDC correction strength; Paragraphs 0056/0057, marking and assigning a spare row based on an error being repetitive based on a predetermined threshold), in response to operating in a self-refreshing mode (Paragraph 0058, the actual repair may occur when the DRAM enters a power-down-self-refresh mode), the first redundancy word line corresponding to the first word line among the plurality of redundancy word lines (Paragraph 0037, when mapping a spare row, the spare row is mapped to the corresponding original row).
Ware does not expressly teach:
that the host comprises a central processing unit (Ware is focused on the memory controller/memory and not the system using it);
nor that the self-refreshing mode is prompted by a self-refresh command provided from the central processing unit.
Utsumi teaches a memory controller which starts a self-refreshing mode, including:
a host comprising a central processing unit (Paragraph 0029, the controller of the controller unit is a CPU); and
a self-refresh command provided from the central processing unit to operate in a self-refreshing mode (Paragraph 0105, the CPU issues a self-refresh command to SDRAM when it enters a power-saving mode).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the host of Ware to include a CPU. The examiner takes official notice that a CPU is a common and well-known computer component used to perform processes. It would be clear to one of ordinary skill in the art that, if the system of Ware is embodied as described in its paragraph 0067 (Media that may be processed by a processing entity within the computer system), then it would likely be in part embodied by a CPU.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the self-refreshing mode of Ware would be started in response to a self-refresh command provided from the CPU as taught by Utsumi. It would have been obvious because Ware describes that the repair can be performed in a self-refresh mode, but does not disclose implementation details. One of ordinary skill in the art would be drawn to known art for implementation details for a self-refresh mode, and would recognize a command sent by a CPU as a common method of controlling a component. Utsumi in particular would be considered because it is to applying self-refresh while the device is powering down, similarly to Ware.
Regarding claim 2, Ware in view of Utsumi teaches the semiconductor device of claim 1, wherein the host further comprises:
a physical layer connected between the controller and the memory device (Ware Fig. 1, the interface logics 108, 110, 112, 114, 124, and 126, and the bus 106), the physical layer being configured to transmit and receive a repair command (Ware paragraph 0038, commands transmitted which connect to repair mapping structures; Ware paragraph 0051, an activate command which is part of a repair method), a data command (Ware paragraph 0038, commands to access memory banks; Ware paragraph 0047, a command to write), an address, and data to and from the memory device (Ware paragraph 0022, the transfer of data, command, and address signals directed by the memory controller) through a command/address channel (Ware paragraph 0022, the C/A interface 0022 and data interface 112).
Regarding claim 3, Ware in view of Utsumi teaches the semiconductor device of claim 2, wherein the controller is configured to, based on the number of the occurrence of the first type of error in the first memory cell exceeding the predetermined threshold value, determine whether the first memory cell row is in an idle state (Ware paragraph 0058, the repair waits until the DRAM enters the power-down-self-refresh mode; Utsumi paragraph 0104, the condition to enter the power-saving mode is determining that the apparatus is idle), and
wherein the controller is configured to, based on a determination that the first memory cell row is in the idle state, deactivate the first word line and activate the first redundancy word line (In the combination of Ware and Utsumi applied to claim 1, Ware enters its self-refresh mode through the process taught by Utsumi, and as stated in Ware paragraph 0058, does not perform repair until it is in the self-repair mode. Therefore Ware will only perform the repair of replacing the redundant word line based on the determination in the process taught by Utsumi).
Regarding claim 9, Ware in view of Utsumi teaches the semiconductor device of claim 1, wherein the controller is configured to, in a state in which the first word line is deactivated and the first redundancy word line is activated, block the first word line in response to a shutdown and cut off a power supplied to the memory device (Ware paragraph 0058, the repair may be applied during a power-down-self-refresh, when power is removed from the memory, blocking off the faulty memory).
Ware in view of Utsumi as applied to claim 1 does not explicitly teach that the shutdown is prompted by a shutdown command provided by the central processing unit.
Utsumi teaches that the shutdown is prompted by a shutdown command provided by the central processing unit (Fig. 5 and paragraphs 0106 – 0113, the CPU sends a number of signals to the information processing apparatus’s power control unit to turn it off).
It would be obvious to one of ordinary skill in the art that the shutdown of Ware would be prompted by a shutdown command sent by the CPU as taught by Utsumi. It would be obvious because Ware teaches a shutdown, but does not disclose implementation details for it. One of ordinary skill in the art would be drawn to known art for implementation details for shutting down a component, and would recognize a command sent by a CPU as a common method of controlling a component. Furthermore it would be clear to one of ordinary skill in the art that, considering the system of Ware performs operations in response to shutting down, there should be some signal allowing these operations to be performed at the proper time.
Regarding claim 10, Ware in view of Utsumi teaches the semiconductor device of claim 1, wherein the memory device comprises a plurality of memory dies (Ware paragraphs 0021 and 0023; Figs. 1 – 3).
Claim 11 recites similar language to claim 1, and is similarly rejected.
Regarding claim 12, Ware in view of Utsumi teaches the method of claim 11, further comprising:
blocking a first data command from being applied to the memory device, based on the number of the occurrence of the first type of error in the first memory cell row exceeding the predetermined threshold value (Ware paragraph 0055, if the failed cell is to be repaired, the accessed data is to be corrected at the controller or a remedial read, rather than the memory device, that is, the original data command is corrected before being applied to the memory device; Ware paragraph 0057, data storage is redirected away from the original address); and
deactivating the first word line and activating the first redundancy word line, based on the first memory cell row being in an idle state (In the combination of Ware and Utsumi applied to claim 1, Ware enters its self-refresh mode through the process taught by Utsumi, and as stated in Ware paragraph 0058, does not perform repair until it is in the self-repair mode. Therefore Ware will only perform the repair of replacing the redundant word line based on the determination in the process taught by Utsumi).
Claim 15 recites similar language to claim 9, and is similarly rejected.
Claim 16 recites similar language to claim 1, and is similarly rejected.
Regarding claim 17, Ware in view of Utsumi teaches the semiconductor device of claim 16, wherein the host is configured to, based on the detected error being of the first type, correct the first type of error in the first memory cell row using the error correction code (Ware Paragraph 0036, the system may be configured such that if the error is minor/single-bit, the error is corrected via the error detection and correction code).
Claim 18 recites similar language to claim 12, and is similarly rejected.
Claim 19 recites similar language to claims 2 and 10, and is similarly rejected.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ware in view of Utsumi, further in view of Iwasaki et al. (US Patent Application Publication 2012/0011303), hereinafter Iwasaki.
Regarding claim 4, Ware in view of Utsumi teaches the semiconductor device of claim 3, wherein the controller is configured to, based on a determination that the first memory cell row is not in the idle state, wait to allow the first memory cell row to transition to the idle state (Utsumi Fig. 7, if the memory is not in an idle state, the flowchart will continue following the NO arrow from S701 to itself).
Ware in view of Utsumi does not teach to block a first data command from being applied to the first memory cell row to allow the first memory cell row to transition to the idle state (Utsumi will wait for the system to be idle before powering down, or wait until receiving a command. It does not disclose implementation details regarding active data commands when it is shutting down. Ware teaches powering down, but does not disclose implementation details).
Ware, however, teaches that a process that produces data commands may be stopped in response to a failure (Paragraph 0062). This would involve blocking the data commands of the process from being performed.
Iwasaki teaches a memory controller in which, in response to a shutdown command from the CPU, the memory device stops receiving commands from the host and discards other commands (Paragraph 0065).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invetion that, if the system of Ware in view of Utsumi was to be powered down, then the active processes, and by extension their data commands, should be blocked to allow the system to transition to the idle state as taught by Iwasaki. It would be obvious because if an operator intends to shut down the memory, then any further data commands would be undesirable to the operator. One of ordinary skill in the art would understand the benefits of halting executing processes in the case of a controlled shutdown.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ware in view of Utsumi, further in view of Kurkowski (US Patent 5,235,548, cited in previous action).
Regarding claim 6, Ware in view of Utsumi teaches the semiconductor device of claim 2, wherein the controller is configured to block the first word line based on an occurrence of a second type of error that is uncorrectable through the ECC in the first memory cell (Ware paragraph 0057, the repair logic redirects data storage from the original failed address. This is based on the “hard” errors described in Ware paragraph 0044).
Ware in view of Utsumi does not explicitly teach to cut off a power supplied to the memory device.
Kurkowski teaches to cut off a power supplied to the memory device when a row is defective in a memory with redundant rows (Abstract, column 2 line 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to, in the system of Ware in view of Utsumi, cut off a power supplied to the memory device, as taught by Kurkowski. One would be motivated to do so as it provides the benefit of higher power efficiency (Kurkowski column 1 line 59 – Column 2 line 20). It would be clear to one of ordinary skill in the art that, if it is known that a row has a serious error, it would not be necessary to continue providing it power after it has been replaced, because it is no longer in use.
Claims 7, 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ware in view of Utsumi and Kurkowski, further in view of Huang et al. (US Patent 6,640,321), hereinafter Huang.
Regarding claim 7, Ware in view of Utsumi and Kurkowski teaches the semiconductor device of claim 6, wherein the controller is configured to, based on the occurrence of the second type of error in the first memory cell row, deactivate the first word line and activate the first redundancy word line (Ware paragraphs 0056/0057, marking and assigning a spare row), and block the first word line (Ware paragraph 0057, the repair logic redirects data storage from the original failed address. This is based on the “hard” errors described in Ware paragraph 0044).
Ware in view of Utsumi and Kurkowski does not teach that this is based on data written in a first redundancy memory cell row connected to the first redundancy word line of the second memory cell array being equal to data read from the first redundancy memory cell row (While a spare row would need to be usable to replace a row, Ware does not expressly indicate how this is determined).
Huang teaches that it is conventional to test spare rows (Column 2 lines 5 – 22) by writing data to the spare row, and then reading it to confirm it is equal to the data read (Column 1 line 65 – Column 2 line 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the repair logic of Ware would test its spare resources before using them in the manner taught by Huang. It would be obvious because, as would be clear to one of ordinary skill in the art, a defective spare row should not be used. One of ordinary skill in the art would be driven to use well-known and conventional methods of testing spare rows, such as that disclosed by Huang.
Regarding claim 8, Ware in view of Utsumi, Kurkowski and Huang teaches the semiconductor device of claim 7, wherein the controller is configured to, based on the occurrence of the second type of error in the first memory cell row, determine whether the first redundancy memory cell row corresponding to the first memory cell row is available in the second memory cell array and activate the first redundancy word line connected to the first redundancy memory cell row based on a determination that the first redundancy memory cell row is available (Ware paragraph 0034, spare elements are used in available; Huang column 2 lines 5 – 8, a faulty row is replaced by the first available replacement row).
Claim 14 recites similar language to claim 7, and is similarly rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN PAI SONG HUANG whose telephone number is (571)272-0510. The examiner can normally be reached Monday - Friday 11:30 AM - 8:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ASHISH THOMAS can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.P.H./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
Prosecution Insights