DETAILED ACTION
This Office Action is in response to the Applicant’s Amendment filed on 07/20/2026. In virtue of the amendment:
Claims 1-20 are pending in the instant application.
Claims 1-3, 9, 12, 19 and 20 are currently amended.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 07/20/2026, with respect to the rejection(s) of claim(s) 1-20 have been fully considered and are persuasive. However, upon further consideration, a new ground(s) of rejection is made in view of Hammond (U.S. Pub. 2022/0115206 A1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 7, 12, 13 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goto (U.S. Pub. 2007/0017636 A1) in view of Hammond (U.S. Pub. 2022/0115206 A1).
Regarding claim 1, Goto discloses a semiconductor wafer processing apparatus (Figs. 1-30), comprising:
a plasma chamber (2, Fig. 1, Abstract);
a processing chamber (14, Fig. 1, par [0073]) connected to the plasma chamber and comprising an electrostatic chuck (11, Fig. 1) configured to support a semiconductor wafer (12, Fig. 1, par [0072]);
a plurality of grid electrodes (4b, Figs. 3, 4, 6, 7; cathode and anode electrodes, Figs. 8-10A, 13-19) between the plasma chamber (2) and the processing chamber (14); and
through-holes (3, Figs. 1-3, Abstract) extending through the plurality of grid electrodes (Figs. 1-3),
wherein the plurality of grid electrodes comprise a first grid electrode (e.g., cathode electrodes) and a second grid electrode (anode electrodes) spaced apart from the first grid electrode in a direction from the plasma chamber (2) to the processing chamber (14) (Figs. 8-10A, 13-19),
wherein at least one of the first grid electrode and the second grid electrode comprises a plurality of electrode plates (as plate shape 4 in Fig. 2, par [0005]), and
wherein voltages having different potential differences are respectively applied to the plurality of electrode plates (when the potentials to be applied to the respective electrodes are made different, par [0100]. Figs. 14).
Goto does not teach a first electrode plate, and a second electrode plate surrounding an outer periphery of the first electrode plate.
However, as evidenced by Hammond, providing the first electrode plate (404, Fig. 4), and the second electrode plate (402, Fig. 4) surrounding an outer periphery of the first electrode plate (Fig. 4, par [0034]) is well known in the art.
Therefore, it would have been obvious to one having skill in the art before the filing date of the invention to employ the plasma apparatus of Goto with the electrodes as taught by Hammond in order to control and balance the RF energy supplied to the processing chamber.
Regarding claim 2, Goto/Hammond discloses the semiconductor wafer processing apparatus wherein at least one of the first grid electrode (cathode) and the second grid electrode (anode) is buried in an insulator (insulator, Figs. 8-10A, 13-19 of Goto).
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Regarding claim 4, Goto/Hammond discloses the semiconductor wafer processing apparatus wherein the insulator comprises a plurality of insulating plates (Fig. 8 of Goto attached above),
wherein the plurality of insulating plates comprise a first insulating plate (1st insulator, Fig. 8 of Goto above), a second insulating plate (2nd insulator, Fig. 8 of Goto), a third insulating plate (3rd insulator, Fig. 8 of Goto), and a fourth insulating plate (4th insulator, Fig. 8 of Goto) sequentially arranged in the direction from the plasma chamber to the processing chamber (Fig. 8 of Goto),
wherein the plurality of grid electrodes further comprise a third grid electrode (e.g., anode electrode and/or cathode electrode (C), Fig. 8 of Goto),
wherein the first grid electrode (e.g., anode electrode, Fig. 8 of Goto) is between the first insulating plate (1st) and the second insulating plate (2nd) (Fig. 8 of Goto),
wherein the second grid electrode (e.g., cathode electrode (B), Fig. 8 of Goto) is between the second insulating plate (2nd) and the third insulating plate (3rd) (Fig. 8 of Goto), and
wherein the third grid electrode is (e.g., anode electrode, Fig. 8 of Goto) between the third insulating plate (3rd) and the fourth insulating plate (4th) (Fig. 8 of Goto).
Regarding claim 7, Goto/Hammond discloses the semiconductor wafer processing apparatus wherein a first voltage (e.g., 175V, Fig. 14 of Goto) is applied to the first grid electrode (cathode electrode (A), Fig. 14 of Goto) and a second voltage (e.g., 350V, Fig. 14 of Goto) is applied to the second grid electrode (cathode electrode (C), Fig. 14 of Goto), wherein the first voltage is different from the second voltage (Fig. 14 of Goto), and wherein a potential difference between the first grid electrode and the second grid electrode is 4 kV or less (less than 4kV, Fig. 14 of Goto).
Regarding claim 12, Goto discloses a semiconductor wafer processing apparatus (Figs. 1-30) comprising:
a plasma chamber (2, Fig. 1, Abstract) in which ions are generated (par [0093]);
a processing chamber (14, Fig. 1, par [0073]) configured to process a semiconductor wafer (12, Fig. 1, par [0072]) using ions generated in the plasma chamber;
an ion extraction device (3, 4, Fig. 3, par [0070]) configured to extract and accelerate ions in the plasma chamber and comprising a plurality of grid electrodes (4b, Figs. 3, 4, 6, 7; cathode and anode electrodes, Figs. 8-10A, 13-19); and
through-holes (3, Figs. 1-3, Abstract) extending through the plurality of grid electrodes (Figs. 1-3),
wherein the plurality of grid electrodes comprise a first grid electrode (e.g., cathode electrodes) and a second grid electrode (e.g., anode electrodes) spaced apart from the first grid electrode in a direction from the plasma chamber (2) to the processing chamber (14),
wherein at least one of the first grid electrode and the second grid electrode comprises a plurality of electrode plates (as plate shape 4 in Fig. 2, par [0005]), and
wherein voltages having different potential differences are applied to the plurality of electrode plates, respectively (when the potentials to be applied to the respective electrodes are made different, par [0100]. Figs. 14).
Goto does not teach a first electrode plate, and a second electrode plate surrounding an outer periphery of the first electrode plate.
However, as evidenced by Hammond, providing the first electrode plate (404, Fig. 4), and the second electrode plate (402, Fig. 4) surrounding an outer periphery of the first electrode plate (Fig. 4, par [0034]) is well known in the art.
Therefore, it would have been obvious to one having skill in the art before the filing date of the invention to employ the plasma apparatus of Goto with the electrodes as taught by Hammond in order to control and balance the RF energy supplied to the processing chamber.
Regarding claim 13, Goto/Hammond discloses the semiconductor wafer processing apparatus wherein the plurality of grid electrodes (cathode, anode, Figs. 8-10A, 13-19 of Goto) are buried in an insulator (insulator, Figs. 8-10A, 13-19 of Goto),
wherein the insulator comprises a plurality of insulating plates (Fig. 8 of Goto attached above),
wherein the plurality of insulating plates comprise a first insulating plate (1st insulator, Fig. 8 of Goto above), a second insulating plate (2nd insulator, Fig. 8 of Goto), a third insulating plate (3rd insulator, Fig. 8 of Goto), and a fourth insulating plate (4th insulator, Fig. 8 of Goto) sequentially arranged in the direction from the plasma chamber to the processing chamber (Fig. 8 of Goto),
wherein the plurality of grid electrodes further comprise a third grid electrode (e.g., anode electrode and/or cathode electrode (C), Fig. 8 of Goto),
wherein the first grid electrode (e.g., anode electrode, Fig. 8 of Goto) is between the first insulating plate (1st) and the second insulating plate (2nd) (Fig. 8 of Goto),
wherein the second grid electrode (e.g., cathode electrode (B), Fig. 8 of Goto) is between the second insulating plate (2nd) and the third insulating plate (3rd) (Fig. 8 of Goto), and
wherein the third grid electrode is (e.g., anode electrode, Fig. 8 of Goto) between the third insulating plate (3rd) and the fourth insulating plate (4th) (Fig. 8 of Goto).
Regarding claim 17, Goto/Hammond discloses the semiconductor wafer processing apparatus wherein a first voltage (e.g., 175V, Fig. 14 of Goto) is applied to the first grid electrode (cathode electrode (A), Fig. 14 of Goto) and a second voltage (e.g., 350V, Fig. 14 of Goto) is applied to the second grid electrode (cathode electrode (C), Fig. 14 of Goto), wherein the first voltage is different from the second voltage (Fig. 14 of Goto), and wherein a potential difference between the first grid electrode and the second grid electrode is 4 kV or less (less than 4kV, Fig. 14 of Goto).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goto/Hammond, as applied above, in view of HORI (WO 2008123196 A1).
Regarding claim 8, Goto/Hammond discloses all of the limitations as claimed except a reflector below the plurality of grid electrodes.
However, as evidenced by HORI, providing the reflector (lens 50, Fig. 2, Abstract) below the plurality of grid electrodes (44, 45, Fig. 2, Abstract) is well known in the art.
Therefore, it would have been obvious to one having skill in the art before the filing date of the invention to employ the apparatus of Goto/Hammond with the reflector as taught by HORI in order to cause discharge gas to be reflected to allow gas to reach the wafer.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goto/Hammond, as applied above.
Regarding claim 11, Goto/Hammond discloses the plurality of electrode plates (4b, Figs. 1-7 of Goto) are separated by a circular gap (as circular in Fig. 2, and gap/space 4a, Figs. 3, 4, 6 and 7 of Goto), and/or the electrode plates (402 and 404, Fig. 4 of Hammond) are separated by a circular gap (gap/space between 402 and 404, Fig. 4 of Hammond).
Goto/Hammond does not teach the circular gap is in a range of 0.5 mm to 4 mm.
However, this limitation is not of the patentable merits since adjusting the gap of electrode plates would have been held obvious to one having skill in the art to prevent of leakage between the electrodes or abnormal discharge (… the material, size, thickness, and the like of the porous spacer member 4a are not particularly limited. In terms of prevention of leakage between the electrodes or abnormal discharge, the porous spacer member 4a preferably has the following arrangement, par [0079] of Goto).
Accordingly, employing the apparatus of Goto/Hammond with the circular gap having the range of 0.5 mm to 4 mm would have been deemed obvious to one having skill in the art.
Allowable Subject Matter
Claim 20 is allowed.
The reasons for the allowance of claim 12 have been indicated in previous Office Action mailed on 04/28/2026.
Claims 3, 5, 6, 9, 10, 14-16, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Inquiry
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIMMY T VU whose telephone number is (571)272-1832. The examiner can normally be reached on 9:00 AM - 6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H. Taningco can be reached on 571-272-8048. The fax phone numbers for the organization where this application or proceeding is assigned are 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2800.
/JIMMY T VU/Primary Examiner, Art Unit 2845
