DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to communication(s) filed on 01/10/2025. Claims 1-20 have been examined and are pending in this Office Action.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 Analysis: Claims 1-20 are within the four statutory categories. Claims 1-13 are drawn to a device, which is within the four statutory categories (i.e., apparatus). Claims 14-20 are drawn to a method, which is within the four statutory categories (i.e., process).
Regarding claim 1,
Step 2A Prong 1: The claim recites multiple abstract ideas as explained below. The claim recites:
wherein, the first circuit is configured to: convert the first command into a second command – This limitation, as drafted, is a process that, under its broadest reasonable interpretation, cover the abstract idea(s) of a mental process because they recite a process that could be practically performed in the human mind.
perform an operation on first data based on the second command – This limitation, as drafted, is a process that, under its broadest reasonable interpretation, cover the abstract idea(s) of a mental process because they recite a process that could be practically performed in the human mind.
Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
a first circuit – The additional element of “a first circuit”, as drafted, is reciting generic computer components. The generic computer component in these steps are recited at a high level of granularity (i.e., a generic computer component).
an interface for receiving a first command from a second device – The additional element of “an interface for receiving a first command from a second device”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
receive the first command from the second device over the interface – The additional element of “receive the first command from the second device over the interface”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components. The additional elements amount to no more than adding insignificant extra-solution activity to the judicial exception.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 2,
Step 2A Prong 1: The claim depends from claim 1. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the second device includes at least one of a processor or a memory controller - The additional element of “a processor” or “a memory controller”, as drafted, is reciting generic computer components. The generic computer component in these steps are recited at a high level of granularity (i.e., a generic computer component).
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 3,
Step 2A Prong 1: The claim depends from claim 1. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the interface includes a control bus and a data bus, wherein the first command is received via the control bus - The additional element of “wherein the interface includes a control bus and a data bus, wherein the first command is received via the control bus”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 4,
Step 2A Prong 1: The claim depends from claim 3. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein a memory address associated with the first command is received via the data bus - The additional element of “wherein a memory address associated with the first command is received via the data bus”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 5,
Step 2A Prong 1: The claim depends from claim 1. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the first command from the second device includes a memory access command, and the second command includes an instruction to perform a computation on the first data - The additional element of “wherein the first command from the second device includes a memory access command, and the second command includes an instruction to perform a computation on the first data”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 6,
Step 2A Prong 1: The claim depends from claim 5. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the first circuit includes an arithmetic logic unit, and the computation includes an arithmetic operation - The additional element of “wherein the first command from the second device includes a memory access command, and the second command includes an instruction to perform a computation on the first data”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 7,
Step 2A Prong 1: The claim depends from claim 6. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the first circuit includes a switch for transmitting the first data to the arithmetic logic unit - The additional element of “wherein the first circuit includes a switch for transmitting the first data to the arithmetic logic unit”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 8,
Step 2A Prong 1: The claim depends from claim 1. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
further comprising a memory medium, wherein the first circuit is configured to transmit a data access command to the memory medium, wherein the data access command is associated with the second command - The additional element of “further comprising a memory medium, wherein the first circuit is configured to transmit a data access command to the memory medium, wherein the data access command is associated with the second command”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 9,
Step 2A Prong 1: The claim depends from claim 8. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the data access command is for retrieving the first data stored in the memory medium - The additional element of “wherein the data access command is for retrieving the first data stored in the memory medium”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 10,
Step 2A Prong 1: The claim depends from claim 8. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the data access command is for storing second data in the memory medium based on the operation on the first data - The additional element of “wherein the data access command is for storing second data in the memory medium based on the operation on the first data”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 11,
Step 2A Prong 1: The claim depends from claim 1. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the interface comprises: a first connection for receiving, from the second device, a first packet including the first command; and a second connection for transmitting a second packet from the first circuit to the second device - The additional element of “wherein the interface comprises: a first connection for receiving, from the second device, a first packet including the first command; and a second connection for transmitting a second packet from the first circuit to the second device”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 12,
Step 2A Prong 1: The claim depends from claim 11. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the first packet comprises an instruction to perform a computation on the first data - The additional element of “wherein the first packet comprises an instruction to perform a computation on the first data”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 13,
Step 2A Prong 1: The claim depends from claim 12. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the first packet comprises a bit for transmitting the instruction to the first circuit - The additional element of “wherein the first packet comprises a bit for transmitting the instruction to the first circuit”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 14,
Step 2A Prong 1: The claim recites multiple abstract ideas as explained below. The claim recites:
converting, by the first circuit, the first command into a second command – This limitation, as drafted, is a process that, under its broadest reasonable interpretation, cover the abstract idea(s) of a mental process because they recite a process that could be practically performed in the human mind.
performing, by the first circuit, an operation on first data based on the second command – This limitation, as drafted, is a process that, under its broadest reasonable interpretation, cover the abstract idea(s) of a mental process because they recite a process that could be practically performed in the human mind.
Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
receiving, by an interface, a first command from a second device – The additional element of “an interface for receiving a first command from a second device”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
receiving the first command by a first circuit coupled to the interface – The additional element of “an interface for receiving a first command from a second device”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components. The additional elements amount to no more than adding insignificant extra-solution activity to the judicial exception.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 15,
Step 2A Prong 1: The claim depends from claim 14. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the interface includes a control bus and a data bus, wherein the first command is received via the control bus - The additional element of “wherein the interface includes a control bus and a data bus, wherein the first command is received via the control bus”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 16,
Step 2A Prong 1: The claim depends from claim 15. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein a memory address associated with the first command is received via the data bus - The additional element of “wherein a memory address associated with the first command is received via the data bus”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 17,
Step 2A Prong 1: The claim depends from claim 14. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the first command from the second device includes a memory access command, and the second command includes an instruction to perform a computation on the first data - The additional element of “wherein the first command from the second device includes a memory access command, and the second command includes an instruction to perform a computation on the first data”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 18,
Step 2A Prong 1: The claim depends from claim 17. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the first circuit includes an arithmetic logic unit, and the computation includes an arithmetic operation - The additional element of “wherein the first circuit includes an arithmetic logic unit, and the computation includes an arithmetic operation”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 19,
Step 2A Prong 1: The claim depends from claim 18. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
wherein the first circuit includes a switch for transmitting the first data to the arithmetic logic unit - The additional element of “wherein the first circuit includes a switch for transmitting the first data to the arithmetic logic unit”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 20,
Step 2A Prong 1: The claim depends from claim 14. So it is directed to the same abstract idea(s). Accordingly, the claim is directed to an abstract idea.
Step 2A Prong 2: The claim recites the additional elements of:
further comprising: transmitting a data access command to a memory medium, wherein the data access command is associated with the second command - The additional element of “further comprising: transmitting a data access command to a memory medium, wherein the data access command is associated with the second command”, as drafted, is reciting generic computer components. The generic computer components in these steps are recited at a high level of generality (i.e., as a generic computer component performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component [see MPEP §2106.05(f)].
Accordingly, the claims do not include any additional elements that would integrate the judicial exception into a practical application.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong 2, the additional elements amount to no more than applying an exception using generic computer components.
Accordingly, the additional elements are not sufficient to amount to significantly more than the judicial exception. The claim is not patent eligible.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
As enumerated in the table below, instant claims 1, 5-7, 11, 14, and 17-19 are anticipated by claims 1-4, 11, and 13 of US Patent 12,197,726.
Status
Instant Application
US Patent 12,197,726
Anticipation
1. A memory device comprising: a first circuit; and an interface for receiving a first command from a second device, wherein, the first circuit is configured to: receive the first command from the second device over the interface; convert the first command into a second command; and perform an operation on first data based on the second command.
1. A memory device comprising: a first circuit; and an interface for receiving a first command to configure the memory device, wherein the memory device is configured to operate in a first mode based on the first command including a first value, and configured to operate in a second mode based on the first command including a second value, wherein based on the memory device operating in the first mode, the first circuit is configured to receive a second command and translate the second command into a third command, wherein the third command is for performing computation of first data.
Obvious in view of Resnick US 2015/0143040
2. The memory device of claim 1, wherein the second device includes at least one of a processor or a memory controller.
Claim 1
Obvious in view of Resnick US 2015/0143040
3. The memory device of claim 1, wherein the interface includes a control bus and a data bus, wherein the first command is received via the control bus.
Claim 1
Obvious in view of Resnick US 2015/0143040
4. The memory device of claim 3, wherein a memory address associated with the first command is received via the data bus.
Claim 1
Anticipation
5. The memory device of claim 1, wherein the first command from the second device includes a memory access command, and the second command includes an instruction to perform a computation on the first data.
Claim 1
Anticipation
6. The memory device of claim 5, wherein the first circuit includes an arithmetic logic unit, and the computation includes an arithmetic operation.
2. The memory device of claim 1, wherein the first circuit includes at least one of a switch or an arithmetic logic unit.
Anticipation
7. The memory device of claim 6, wherein the first circuit includes a switch for transmitting the first data to the arithmetic logic unit.
4. The memory device of claim 3, wherein the first packet comprises an instruction to instruct the switch or the arithmetic logic unit to perform the computation of the first data.
Obvious in view of Resnick US 2015/0143040
8. The memory device of claim 1 further comprising a memory medium, wherein the first circuit is configured to transmit a data access command to the memory medium, wherein the data access command is associated with the second command.
Claim 1
Obvious in view of Resnick US 2015/0143040
9. The memory device of claim 8, wherein the data access command is for retrieving the first data stored in the memory medium.
Claim 1
Obvious in view of Resnick US 2015/0143040
10. The memory device of claim 8, wherein the data access command is for storing second data in the memory medium based on the operation on the first data.
Claim 1
Anticipation
11. The memory device of claim 1, wherein the interface comprises: a first connection for receiving, from the second device, a first packet including the first command; and a second connection for transmitting a second packet from the first circuit to the second device.
3. The memory device of claim 2, wherein the interface comprises: a first connection for receiving, from a computing device, a first packet including one of the first command or the second command; and a second connection for transmitting a second packet from the first circuit to the computing device.
Obvious in view of HMC Spec
12. The memory device of claim 11, wherein the first packet comprises an instruction to perform a computation on the first data.
Claim 1
Obvious in view of HMC Spec
13. The memory device of claim 12, wherein the first packet comprises a bit for transmitting the instruction to the first circuit.
Claim 1
Anticipation
14. A method comprising: receiving, by an interface, a first command from a second device; receiving the first command by a first circuit coupled to the interface; converting, by the first circuit, the first command into a second command; and performing, by the first circuit, an operation on first data based on the second command.
11. A method comprising: receiving a first command to configure a memory device, wherein the memory device is configured to operate in a first mode based on the first command being associated with a first value, and configured to operate in a second mode based on the first command being associated with a second value; receiving a second command; based on the memory device being configured to operate in the first mode: translating the second command into a third command; and performing computation of first data based on the third command.
Obvious in view of Resnick US 2015/0143040
15. The method of claim 14, wherein the interface includes a control bus and a data bus, wherein the first command is received via the control bus.
Claim 11
Obvious in view of Resnick US 2015/0143040
16. The method of claim 15, wherein a memory address associated with the first command is received via the data bus.
Claim 11
Anticipation
17. The method of claim 14, wherein the first command from the second device includes a memory access command, and the second command includes an instruction to perform a computation on the first data.
Claim 11
Anticipation
18. The method of claim 17, wherein the first circuit includes an arithmetic logic unit, and the computation includes an arithmetic operation.
13. The method of claim 12, wherein the arithmetic operation is performed by an arithmetic logic unit of the memory device.
Anticipation
19. The method of claim 18, wherein the first circuit includes a switch for transmitting the first data to the arithmetic logic unit.
13. The method of claim 12, wherein the arithmetic operation is performed by an arithmetic logic unit of the memory device.
Obvious in view of Resnick US 2015/0143040
20. The method of claim 14 further comprising: transmitting a data access command to a memory medium, wherein the data access command is associated with the second command.
Claim 11
Claims 2-4, 8-10, 15-16, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,197,726 in view of Resnick US 2015/0143040 (“Resnick”).
As per dependent claim 2, Resnick teaches wherein the second device includes at least one of a processor (“The computer system 10 includes several parallel processors 14.sub.1-N connected to a common processor bus 16.” Para 0010 and FIG. 1) or a memory controller (“in response to a command from the memory controller 44, the select circuit 54 routes data from the Boolean Logic 60 to the write drivers 56.” Para 0016 and FIG. 2).
Given the teaching of Resnick, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent 12,197,726 with “wherein the second device includes at least one of a processor or a memory controller”.
As per dependent claims 3 and 15, taking claim 3 as exemplary, Resnick teaches wherein the interface includes a control bus and a data bus, wherein the first command is received via the control bus (“The system memory 40 is controlled by memory controller circuitry 44 in the system controller 20 through a memory bus 46, which normally includes a command/status bus, an address bus and a data bus.” Para 0012 and FIG. 1).
Given the teaching of Resnick, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent 12,197,726 with “wherein the interface includes a control bus and a data bus, wherein the first command is received via the control bus”.
As per dependent claims 4 and 16, taking claim 4 as exemplary, Resnick teaches wherein a memory address associated with the first command is received via the data bus (“The system memory 40 is controlled by memory controller circuitry 44 in the system controller 20 through a memory bus 46, which normally includes a command/status bus, an address bus and a data bus.” Para 0012 and FIG. 1).
Given the teaching of Resnick, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent 12,197,726 with “wherein a memory address associated with the first command is received via the data bus”.
As per dependent claims 8 and 20, taking claim 4 as exemplary, Resnick teaches further comprising a memory medium, wherein the first circuit is configured to transmit a data access command to the memory medium, wherein the data access command is associated with the second command (“In response to a read command, the read data are applied to the Boolean Logic 60, and the Boolean Logic 60 then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank 58 where the data was read.” Para 0016 and FIG. 2).
Given the teaching of Resnick, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent 12,197,726 with “further comprising a memory medium, wherein the first circuit is configured to transmit a data access command to the memory medium, wherein the data access command is associated with the second command”.
As per dependent claim 9, Resnick teaches wherein the data access command is for retrieving the first data stored in the memory medium (“In response to a read command, the read data are applied to the Boolean Logic 60, and the Boolean Logic 60 then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank 58 where the data was read.” Para 0016 and FIG. 2).
Given the teaching of Resnick, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent 12,197,726 with “wherein the data access command is for retrieving the first data stored in the memory medium”.
As per dependent claim 10, Resnick teaches wherein the data access command is for storing second data in the memory medium based on the operation on the first data (“In response to a read command, the read data are applied to the Boolean Logic 60, and the Boolean Logic 60 then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank 58 where the data was read.” Para 0016 and FIG. 2).
Given the teaching of Resnick, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent 12,197,726 with “wherein the data access command is for storing second data in the memory medium based on the operation on the first data”.
Claims 12-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,197,726 in view of NPL “Hybrid Memory Cube Specification 2.0”, 2014 (“HMC Spec”).
As per dependent claim 12, HMC Spec teaches wherein the first packet comprises an instruction to perform a computation on the first data (FIG. 14 on page 41 shows the request packet header layout. Bits 0 to 6 are designated for a command (CMD[6:0]) to be transmitted to the responder. See Table 26 on pages 50-52 for the various 6-bit commands).
Given the teaching of HMC Spec, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent 12,197,726 with “wherein the first packet comprises an instruction to perform a computation on the first data”.
As per dependent claim 13, HMC Spec teaches wherein the first packet comprises a bit for transmitting the instruction to the first circuit (FIG. 14 on page 41 shows the request packet header layout. Bits 0 to 6 are designated for a command (CMD[6:0]) to be transmitted to the responder. See Table 26 on pages 50-52 for the various 6-bit commands).
Given the teaching of HMC Spec, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent 12,197,726 with “wherein the first packet comprises a bit for transmitting the instruction to the first circuit”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-10, 14-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Resnick US 2015/0143040 (“Resnick”).
As per independent claim 1, Resnick teaches A memory device (“The computer system 10 … includes system memory 40,” para 0012 and FIG. 1) comprising:
a first circuit (“Boolean Logic 60” para 0015 and FIG. 2. “Although the system 50 shown in FIG. 2 uses Boolean Logic 60, other embodiments may use circuits or logic that perform other increased functions.” Para 0017);
an interface for receiving a first command from a second device (“The system memory 40 is controlled by memory controller circuitry 44 in the system controller 20 through a memory bus 46, which normally includes a command/status bus, an address bus and a data bus.” Para 0012 and FIG. 1), wherein, the first circuit is configured to: receive the first command from the second device over the interface (“in response to a command from the memory controller 44, the select circuit 54 routes data from the Boolean Logic 60 to the write drivers 56.” Para 0016 and FIG. 2);
perform an operation on first data based on the second command (“In response to a read command, the read data are applied to the Boolean Logic 60, and the Boolean Logic 60 then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank 58 where the data was read.” Para 0016 and FIG. 2).
Resnick does not explicitly teach “convert the first command into a second command”.
However, Resnik teaches “In response to a read command, the read data are applied to the Boolean Logic 60, and the Boolean Logic 60 then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank 58 where the data was read.” Para 0016 and FIG. 2. In the above-noted statement of Resnick, a read command is implicitly converted to a logic command and the logic operation is performed on the read data before the modified data is stored back.
Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Resnick with “convert the first command into a second command”. The motivation would be that the disclosure improves system performance architectural scalability at a relatively low cost, para 0006 of Resnick.
As per dependent claim 2, Resnick discloses the device of claim 1. Resnick teaches wherein the second device includes at least one of a processor (“The computer system 10 includes several parallel processors 14.sub.1-N connected to a common processor bus 16.” Para 0010 and FIG. 1) or a memory controller (“in response to a command from the memory controller 44, the select circuit 54 routes data from the Boolean Logic 60 to the write drivers 56.” Para 0016 and FIG. 2).
As per dependent claim 3, Resnick discloses the device of claim 1. Resnick teaches wherein the interface includes a control bus and a data bus, wherein the first command is received via the control bus (“The system memory 40 is controlled by memory controller circuitry 44 in the system controller 20 through a memory bus 46, which normally includes a command/status bus, an address bus and a data bus.” Para 0012 and FIG. 1).
As per dependent claim 4, Resnick discloses the device of claim 3. Resnick teaches wherein a memory address associated with the first command is received via the data bus (“The system memory 40 is controlled by memory controller circuitry 44 in the system controller 20 through a memory bus 46, which normally includes a command/status bus, an address bus and a data bus.” Para 0012 and FIG. 1).
As per dependent claim 5, Resnick discloses the device of claim 1. Resnick teaches wherein the first command from the second device includes a memory access command (“In response to a read command,” para 0016), and the second command includes an instruction to perform a computation on the first data (“In response to a read command, the read data are applied to the Boolean Logic 60, and the Boolean Logic 60 then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank 58 where the data was read.” Para 0016 and FIG. 2).
As per dependent claim 6, Resnick discloses the device of claim 5. Resnick teaches wherein the first circuit includes an arithmetic logic unit, and the computation includes an arithmetic operation (“Although the system 50 shown in FIG. 2 uses Boolean Logic 60, other embodiments may use circuits or logic that perform other increased functions. In general, this increased functionality may be logic functions, such as AND, OR, etc. functions, arithmetic operations, such as ADD and SUB, and similar operations that can update and change the contents of memory.” Para 0017 and FIG. 2).
As per dependent claim 8, Resnick discloses the device of claim 1. Resnick teaches further comprising a memory medium, wherein the first circuit is configured to transmit a data access command to the memory medium, wherein the data access command is associated with the second command (“In response to a read command, the read data are applied to the Boolean Logic 60, and the Boolean Logic 60 then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank 58 where the data was read.” Para 0016 and FIG. 2).
As per dependent claim 9, Resnick discloses the device of claim 8. Resnick teaches wherein the data access command is for retrieving the first data stored in the memory medium (“In response to a read command, the read data are applied to the Boolean Logic 60, and the Boolean Logic 60 then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank 58 where the data was read.” Para 0016 and FIG. 2).
As per dependent claim 10, Resnick discloses the device of claim 8. Resnick teaches wherein the data access command is for storing second data in the memory medium based on the operation on the first data (“In response to a read command, the read data are applied to the Boolean Logic 60, and the Boolean Logic 60 then performs a Boolean logic operation on the read data and writes data resulting from the operation back to the location in the Bank 58 where the data was read.” Para 0016 and FIG. 2).
As per claims 14-18 and 20, these claims are respectively rejected based on arguments provided above for similar rejected claims 1, 3-6, and 8.
Claims 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Resnick in view of Okada et al. US 2005/0134308 (“Okada”).
As per dependent claim 7, Resnick discloses the device of claim 6. Resnick may not explicitly disclose, but in an analogous art in the same field of endeavor, Okada teaches wherein the first circuit includes a switch for transmitting the first data to the arithmetic logic unit (“To pass data from ALUs in upper stages to ones in lower stages, connection switches for switching connection among the ALUs are set to the connection data set, whereby which ALUs in the lower stages to pass the data to are determined. During operation, arithmetic processing is performed in accordance with the configuration information, and the results are output.” Para 0064 and FIG. 1).
Given the teaching of Okada, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Resnick with “wherein the first circuit includes a switch for transmitting the first data to the arithmetic logic unit”. The motivation would be that using a reconfigurable circuit comprising ALUs, it is possible to reduce the number of wires in terms of hardware and reduce such components as switches which achieves power savings, paras 0007-0008 of Okada.
As per dependent claim 19, this claim is rejected based on arguments provided above for similar rejected dependent claim 7.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Resnick in view of NPL “Hybrid Memory Cube Specification 2.0”, 2014 (“HMC Spec”).
As per dependent claim 11, Resnick discloses the device of claim 1. Resnick may not explicitly disclose, but in an analogous art in the same field of endeavor, HMC Spec teaches wherein the interface comprises: a first connection for receiving, from the second device, a first packet including the first command (FIG. 2 on page 10 is a block diagram of HMC (Hybrid Memory Cube) showing that the logic base communicates with requestors using serialized full duplex links (link 0, link 1 etc.). FIG. 3 on page 14 is a more detailed illustration of downstream and upstream links between a requester and a responder (the logic base). Request packets are known to carry request commands from the requestor host to the responder and response packets carry response commands from the responder to the requestor, see pages 41-42);
a second connection for transmitting a second packet from the first circuit to the second device (FIG. 2 on page 10 is a block diagram of HMC (Hybrid Memory Cube) showing that the logic base communicates with requestors using serialized full duplex links (link 0, link 1 etc.). FIG. 3 on page 14 is a more detailed illustration of downstream and upstream links between a requester and a responder (the logic base). Request packets are known to carry request commands from the requestor host to the responder and response packets carry response commands from the responder to the requestor, see pages 41-42).
Given the teaching of HMC Spec, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Resnick with “wherein the interface comprises: a first connection for receiving, from the second device, a first packet including the first command” and “a second connection for transmitting a second packet from the first circuit to the second device”. The motivation would be that it is known in the art that serialized full duplex links achieve improved speed.
As per dependent claim 12, Resnick in combination with HMC Spec discloses the device of claim 11. Resnick may not explicitly disclose, but HMC Spec teaches wherein the first packet comprises an instruction to perform a computation on the first data (FIG. 14 on page 41 shows the request packet header layout. Bits 0 to 6 are designated for a command (CMD[6:0]) to be transmitted to the responder. See Table 26 on pages 50-52 for the various 6-bit commands).
The same motivation that was utilized for combining Resnick and HMC Spec as set forth in claim 11 is equally to claim 12.
As per dependent claim 13, Resnick in combination with HMC Spec discloses the device of claim 12. Resnick may not explicitly disclose, but HMC Spec teaches wherein the first packet comprises a bit for transmitting the instruction to the first circuit (FIG. 14 on page 41 shows the request packet header layout. Bits 0 to 6 are designated for a command (CMD[6:0]) to be transmitted to the responder. See Table 26 on pages 50-52 for the various 6-bit commands).
The same motivation that was utilized for combining Resnick and HMC Spec as set forth in claim 12 is equally to claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132