DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boroditsky et al (Pub 2010/0225403, further referred to as Boroditsky).
As to claim 1, Boroditsky teaches a circuit for synchronizing oscillators (fig 1 and 2), the circuit comprising:
a power supply voltage source (VCC);
at least three oscillators (fig 2, each (10) with SYNC IN connected to SYNC B) having respective crystal inputs connected to a first single node (SYNC B, all the oscillators are electrically “connected” to SYNC B), each of the at least three oscillators comprises a CMOS unbuffered inverter (U1, paragraph 17);
at least three unbuffered output inverters (U2, paragraph 21), each unbuffered output
inverter inverting buffer having a respective input connected to an output of a corresponding
oscillator of the at least three oscillators;
at least three summing resistors (R4), each summing resistor having a first end connected
to an output of a corresponding unbuffered output inverter (R4 is electrically connected to U2) of the at least three unbuffered output inverters inverting buffers; and
a combined output (SYNC A) created by connecting second ends of the at least three summing
resistors to a single second node (the output of the resistor R4 is connected to SYNC A in which all the oscillator (10) which has the input of SYNC B outputs are connected to).
As to claim 2, Boroditsky teaches wherein each of the at least three oscillators
further comprises a CMOS unbuffered inverter (U1), a bias resistor (R1), a crystal (Z1), an output resistor
connecting to the crystal input (R4), a crystal input capacitor (C3), and a crystal output capacitor (C1).
As to claim 3, Boroditsky teaches wherein the crystals of the at least three oscillators having a similar resonant frequency, the input capacitors of the at least three oscillators having a similar first capacitance, the output capacitors of the at least three oscillators having a similar second capacitance, a stray capacitance in the physical implementation of the circuit, and the output resistors of the at least three oscillators having a similar resistance (fig 1 shows the oscillation circuit (10) with fig 2 showing plurality of (10) being used, thus each oscillator will have the same components and values as each 10 should be relatively identical to one another).
As to claim 5, Boroditsky teaches wherein each of the at least three
unbuffered output inverters (U2) comprises a CMOS unbuffered inverter (paragraph 21).
Allowable Subject Matter
Claims 4, 6, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the cited prior art teach or suggest the synchronously without settling time after power up at the outputs as is recited in claim 4, and the combined masks an upset of the oscillators for a discrimination threshold as is recited in claim 6 and 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY M SHIN whose telephone number is (571)270-7356. The examiner can normally be reached M-F 9am-6pm PST.
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/JEFFREY M SHIN/Primary Examiner, Art Unit 2836
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