Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Office Action is in response to claims filed on 7/29/2026 where claims 1-14 are pending and ready for examination.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Applicant's arguments filed 7/29/2026 have been fully considered but they are not persuasive.
The Examiner has reviewed the Applicant’s arguments submitted on 7/29/2026 in their entirety (Pages 7- 10). The arguments are not persuasive as the Applicant has not acknowledged Fairhurst’s teachings in paragraph [0176]:
[0176] “... When packets arrive into an ITM from ingress packet processing, packet data (in cells) is immediately stored in the main packet buffer (e.g., ITM payload buffer). Packet Control information is held in a cell receive block (CRB) while an egress cut-through manager (EB-CTM) determines whether packet data will take the CT path or the SAF path for the packet data.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 6-10, and 13 -14 are rejected under 35 USC 102(a)(1) as being anticipated by Fairhurst (US US 20190334828)
Regarding claim 1, Fairhurst discloses a method for processing cut-through (CT) and store-and-forward (SAF) traffic, the method comprising:
allocating a common packet data buffer for an egress port to store incoming packet data that includes both CT packets and SAF packets, wherein the CT packets and the SAF packets are to be forwarded out of the same egress port (Fairhurst; Fairhurst teaches they hybrid-shared traffic manager architecture of Fig. 5, including shared ingress buffers, scheduler 540, and egress buffe/output port structures, together with [0112] – [0117] describing that the same output port may operate in either CT state or SA state depending on traffic conditions, thereby teaching that both CT packets and SAF packets are forwarded through the same egress port architecture;
see e.g. Fig.5
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[0112] A network switch generally supports two methods of passing packets from input ports to output ports, which are store-and-forward (SAF) and cut-through (CT). Thus, the hybrid-shared traffic manager architecture may also support the SAF switching and the CT switching ...”);
directing SAF packet control data derived from SAF packet data fields of the SAF packets upon receipt onto a control data path defined by a first plurality of processing engines, the SAF control data to arrive at a scheduling logic engine with a first latency after processing by the first plurality of processing engines (Fairhurst; Fairhurst teaches SAF packet control data being processed through the SAF control path using queuing , admission control, controllers, read launchers 550A-550B, and scheduler 540, where the SAF handling incurs greater latency associated with SF buffering and scheduling before transmission;
see e.g. Fig. 5
see e.g. [0046] – [0050], [0097] –[0099], [0124], [0136]
see e.g. [0176] – [0178], [0135]);
directing CT packet control data derived from CT packet data fields of the CT packets upon receipt onto a second control data path, the CT control data to arrive at the scheduling logic engine with a second latency that is less than the first latency after processing in the second control path by a second plurality of processing engines that bypasses at least one or more processing engines among the first plurality of processing engines (Fairhurst; Fairhurst teaches CT packet control data being processed through a CT control path different from the SAF control path, where CT traffic is handled with lower latency than SAF traffic through expedited cut-through handling that bypasses portions of the SAF buffering/scheduling processing performed for SAF traffic before transmission through scheduler 540 and the egress pipeline;
see e.g. [0112] – [0124] and [0136]
see e.g. [0176] – [0178], [0135]);
generating CT packet dequeue requests for the CT packets using the CT packet control data and generating SAF dequeue requests for the SAF packets using the SAF packet control data (Fairhurst; Fairhurst teaches scheduler-generated dequeue requests for CT and SAF traffic using corresponding CT and SAF control information, including issuance, arbitration, and scheduling of read requests used to retrieve buffered packet data for transmission;
see e.g. Fig. 10
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see e.g. [0052] –[0055], [0094] – [0099];
merging the CT packet dequeue requests and the SAF dequeue requests into a merged sequence of dequeue requests (Fairhurst; Fairhurst teaches the handling of both CT and SAF traffic through the same scheduler/read-launcher path toward the same egress output, the CT and SAF requests must be combined into one ordered flow to decide what leaves the port next. Under BRI. that ordered/arbitrated common request flow is the claimed merged sequence of dequeue requests;
see e.g. Fig. 10, [0052] – [0055-, [0094] – [0099])); and
retrieving packet data from the common packet data buffer based on the merged sequence of dequeue requests (Fairhurst; Fairhurst teaches said feature is facilitated by using the read launcher and scheduler to read buffered packet/cell data for transmission through the shared egress pipeline; Fairhurst teaches both CT and SAF traffic are handled through the same scheduler/read launcher transmission flow toward the same output path, the reordered requests function as a merged sequence under BRI, and the resulting buffer reads correspond to retrieving packet data from the common packet data merged sequence.
see e.g. Fig. 10
[0054] In some aspects, to compensate for these scheduling conflicts, the architecture may allow for memory read requests to be delayed and thus to occur out-of-order. In one or more implementations, the cell read requests from the main scheduler 540 may be forwarded to a corresponding read launcher (e.g., read launcher 550A or 550B), which may be a logical block and/or a dedicated hardware component. The read launcher 550A or 550B resolves the memory bank conflicts and can issue a maximum number of non-colliding reads per clock cycle to each ITM's data buffer. One or more read requests of the read requests that collide with each other are held by a corresponding read launcher (e.g., the read launcher 550A or 550B) until later cycles when the one or more read requests can be issued with no collisions. In one example, if a first and second read requests collide with each other, the first read request may be issued during a next cycle and the second read request may be issued during a subsequent cycle after the next cycle. In another example, if a first and second read requests collide with each other, the first read request may be issued during a current cycle and the second read request may be issued during a next cycle. In one or more implementations, the read requests with collisions may be held in temporary request FIFOs (e.g., associated with the read launcher 550A or 550B), allowing the read requests with collisions to be delayed in the Read Launcher without blocking read requests to non-colliding banks. This allows the main scheduler 540 to continue scheduling cells as needed keep up with the output port bandwidth demands without stalling. Hence, using the read launcher 550A or 550B, the cell read requests may be reordered to avoid collisions. For example, while reordering, older read requests may be prioritized over newer read requests.
Regarding claim 2, Fairhurst discloses the method of Claim 1, wherein the control data path includes, and the second control data path excludes, performing one or more of: active queue management operations relating to the one or more SAF queues, or SAF admission check operations (Fairhurst; Fairhurst discerns CT an SAF handling, where SAF traffic undergoes the fuller queuing/buffering/admission-control style processing associated with SAF operation, while CT traffic is handled through the lower latency CT control path that bypasses portions of the SAP processing pipeline, Under BRI, the SAF -related queue management/admission check operations are included in the SAF path and excluded from the CT path because the CT path is expressly descried as different and lower latency relative to SF processing flow;
See e.g. [0112] – [0124], [0136]).
Regarding claim 3, Fairhurst discloses the method of Claim 1, further comprising: in response to receiving an incoming packet, determining whether the incoming packet is eligible as a CT packet (Fairhurst distinguishes between CT packets and SF packets and applies different handling paths and latency behavior to each. Under BRI, the system necessarily determines whether an incoming packet is eligible for CT handling before directing the packet through the CT path or SAF path, otherwise the disclosed CT versus SAF processing could not occur).
Regarding claim 6, Fairhurst discloses the method of Claim 1, wherein the merged sequence of dequeue requests incurs a single data read request to the common packet data buffer each data unit of a CT or SAF packet (Fairhurst teaches scheduler 90 issued red requests that are arbitrated /reordered into a unified dequeue/read request flow for CT and SAF traffic handled through the same egress transmission structure. The resulting scheduled request causes the read launcher to issue a corresponding red operation to retrieve the next buffered data unit for transmission. Under BRI, the unified scheduler-selected read operation corresponds to the claimed single data read requests for CT or SAF packet data forwarded out of the egress port)
Regarding claim 7, Fairhurst discloses the method of Claim 1, wherein a traffic manager includes the scheduling logic engine configured to perform enqueuing and dequeuing operations on both CT and SAF incoming packets for forwarding and a merging logic engine configured to receive CT and SAF dequeue requests from the scheduling logic engine and merge the CT and SAF dequeue requests into the common sequence of dequeue requests ( Fairhurst; Fairhurst teaches scheduler 540 performing enqueue/dequeue and read-request scheduling operations for both CT and SAF traffic through the shared traffic manager architecture. The same scheduler/arbitration logic receives and reorders CT and SAF dequeue/red requests into a unified request flow for transmission through the common egress structure. Under BRFI. the scheduler/arbitration logic corresponds to the claimed merging logic engine configured to merge the CT and SAF dequeue requests into the common sequence of dequeue requests).
Regarding claim 8, Fairhurst discloses a network switching system, comprising:
a buffer manager configured to allocate a common packet data buffer for an egress port to store incoming packet data that includes both CT packets and SAF packets, wherein the CT packets and the SAF packets are to be forwarded out of the same egress port and to retrieve packet data from the common packet data buffer based on a merged sequence of dequeue requests (Fairhurst; Fairhurst teaches they hybrid-shared traffic manager architecture of Fig. 5, including shared ingress buffers, scheduler 540, and egress buffe/output port structures, together with [0112] – [0117] describing that the same output port may operate in either CT state or SA state depending on traffic conditions, thereby teaching that both CT packets and SAF packets are forwarded through the same egress port architecture;
see e.g. Fig.5
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[0112] A network switch generally supports two methods of passing packets from input ports to output ports, which are store-and-forward (SAF) and cut-through (CT). Thus, the hybrid-shared traffic manager architecture may also support the SAF switching and the CT switching ...”
Furthermore, the scheduler/read-launcher architecture arbitrates and reorders CZT and SAF dequeue/read requests into a unified request flow prior to retrieval of packet data from the shared buffer, such that the resulting packet data retrieval is performed based on the merged sequence of dequeue requests )[0054], [0055], Fig. 10);
an ingress packet processor configured to direct SAF packet control data derived from SAF packet data fields of the SAF packets upon receipt onto a control data path defined by a first plurality of processing engines, the SAF control data to arrive at a scheduling logic engine with a first latency after processing by the first plurality of processing engines (Fairhurst; Fairhurst teaches SAF packet control data being processed through the SAF control path using queuing , admission control, controllers, read launchers 550A-550B, and scheduler 540, where the SAF handling incurs greater latency associated with SF buffering and scheduling before transmission;
see e.g. Fig. 5
see e.g. [0046] – [0050], [0097] –[0099], [0124], [0136])
see e.g. [0176] – [0178], [0135]);
wherein the ingress packet processor is further configured to direct CT packet control data derived from CT packet data fields of the CT packets upon receipt onto a second control data path, the CT control data to arrive at the scheduling logic engine with a second latency that is less than the first latency after processing in the second control path by a second plurality of processing engines that bypasses at least one or more processing engines among the first plurality of processing engines(Fairhurst; Fairhurst teaches CT packet control data being processed through a CT control path different from the SAF control path, where CT traffic is handled with lower latency than SAF traffic through expedited cut-through handling that bypasses portions of the SAF buffering/scheduling processing performed for SAF traffic before transmission through scheduler 540 and the egress pipeline;
see e.g. [0112] – [0124] and [0136]
see e.g. [0176] – [0178], [0135]); ;
a scheduling logic engine configured to generate CT packet dequeue requests for the CT packets using the CT packet control data and to generate SAF dequeue requests for the SAF packets using the SAF packet control data(Fairhurst; Fairhurst teaches scheduler-generated dequeue requests for CT and SAF traffic using corresponding CT and SAF control information, including issuance, arbitration, and scheduling of read requests used to retrieve buffered packet data for transmission;
see e.g. Fig. 10
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see e.g. [0052] –[0055], [0094] – [0099]; ; and
a merging logic engine configured to merge the CT packet dequeue requests and the SAF dequeue requests into the merged sequence of dequeue requests (Fairhurst; Fairhurst teaches said feature is facilitated by using the read launcher and scheduler to read buffered packet/cell data for transmission through the shared egress pipeline; Fairhurst teaches both CT and SAF traffic are handled through the same scheduler/read launcher transmission flow toward the same output path, the reordered requests function as a merged sequence under BRI, and the resulting buffer reads correspond to retrieving packet data from the common packet data merged sequence.
see e.g. Fig. 10
[0054] In some aspects, to compensate for these scheduling conflicts, the architecture may allow for memory read requests to be delayed and thus to occur out-of-order. In one or more implementations, the cell read requests from the main scheduler 540 may be forwarded to a corresponding read launcher (e.g., read launcher 550A or 550B), which may be a logical block and/or a dedicated hardware component. The read launcher 550A or 550B resolves the memory bank conflicts and can issue a maximum number of non-colliding reads per clock cycle to each ITM's data buffer. One or more read requests of the read requests that collide with each other are held by a corresponding read launcher (e.g., the read launcher 550A or 550B) until later cycles when the one or more read requests can be issued with no collisions. In one example, if a first and second read requests collide with each other, the first read request may be issued during a next cycle and the second read request may be issued during a subsequent cycle after the next cycle. In another example, if a first and second read requests collide with each other, the first read request may be issued during a current cycle and the second read request may be issued during a next cycle. In one or more implementations, the read requests with collisions may be held in temporary request FIFOs (e.g., associated with the read launcher 550A or 550B), allowing the read requests with collisions to be delayed in the Read Launcher without blocking read requests to non-colliding banks. This allows the main scheduler 540 to continue scheduling cells as needed keep up with the output port bandwidth demands without stalling. Hence, using the read launcher 550A or 550B, the cell read requests may be reordered to avoid collisions. For example, while reordering, older read requests may be prioritized over newer read requests.
Regarding claim 9, claim 9 is rejected based on the same rationale as claim 2;
Regarding claim 10, claim 10 is rejected based on the same rationale as claim 3;
Regarding claim 13, claim 13 is rejected based on the same rationale as claim 6;
Regarding claim 14, claim 14 is rejected based on the same rationale as claim 7;
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 -5 and 11- 12 are rejected under 35 USC 103 as being unpatentable over Fairhurst in view of Shrivastava (US 2013/0243002)
Regarding claim 4, Fairhurst discloses the method of Claim 1, Fairhurst does not expressly disclose wherein the scheduling logic engine assigns first arrival timestamps of the CT packet control data of the CT packets to the CT packets and assigns second arrival timestamps of the SAF packet control data of the SAF packets to the SAF packets.
Shrivastava discloses:
timestamps (Shrivastava;
See e.g. [0035] “ ... the time stamps of the control packets ...”)
Therefore it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Shrivastava’s timestamp metadata associated with control packets. The motivation being the combined solution provides for implementing a known technique resulting in increased efficiencies of packet processing.
Fairhurst in view of Shrivastava discloses:
the scheduling logic engine assigns first arrival timestamps of the CT packet control data of the CT packets to the CT packets and assigns second arrival timestamps of the SAF packet control data of the SAF packets to the SAF packets (The combined solution per Shrivastava as the assignment of timestamps are facilitated per the timestamp metadata with respect to CT and SAF packet processing. Moreover, it would have been obvious to apply such timestamping to the CT and SAF packet control data of the hybrid traffic manager architecture in order to support scheduling, ordering, and latency-aware packet processing)
Shrivastava discloses:
timestamps (Shrivastava;
See e.g. [0035] “ ... the time stamps of the control packets ...”)
Therefore it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Shrivastava’s timestamp metadata associated with control packets. The motivation being the combined solution provides for implementing a known technique resulting in increased efficiencies of packet processing.
Fairhurst in view of Shrivastava discloses:
the scheduling logic engine assigns first arrival timestamps of the CT packet control data of the CT packets to the CT packets and assigns second arrival timestamps of the SAF packet control data of the SAF packets to the SAF packets (Fairhurst already teaches scheduler 540 generating and arbitrating read/dequeue requests for queued CT/SAF/ traffic through the read launcher infrastructure (e.g. [0054] – [0055], Fig. 10). Shrivastava teaches timestamps associated with control packet processing ([0035]). It would have been obvious to use such timestamps within the scheduler infrastructure of Fairhurst to compare arrival timing of CT and SAF control data and select corresponding dequeue/read requests during scheduling cycles because timestamp-based comparison of queued CT and SAF control data would allow schedule 540 to make deterministic dequeue/read-request selection decisions based on packet arrival timing and latency priority, thereby improving ordered scheduling and low-latency traffic handling within the existing CT/SAF queuing architecture)
Regarding claim 5, Fairhurst discloses the method of Claim 1, Fairhurst does not expressly disclose wherein the scheduling logic engine compares a first arrival timestamp of a CT packet control data portion of a CT packet enqueued in the single CT queue with a second arrival timestamp of a selected SAF packet control data portion of a selected SAF packet enqueued in the one or more SAF queues, and in response to the comparison, select one of a CT dequeue request or a SAF dequeue request and generate a read request during a given read clock cycle
Shrivastava discloses:
timestamps (Shrivastava;
See e.g. [0035] “ ... the time stamps of the control packets ...”)
Therefore it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Shrivastava’s timestamp metadata associated with control packets. The motivation being the combined solution provides for implementing a known technique resulting in increased efficiencies of packet processing.
Fairhurst in view of Shrivastava discloses:
wherein the scheduling logic engine compares a first arrival timestamp of a CT packet control data portion of a CT packet enqueued in the single CT queue with a second arrival timestamp of a selected SAF packet control data portion of a selected SAF packet enqueued in the one or more SAF queues, and in response to the comparison, select one of a CT dequeue request or a SAF dequeue request and generate a read request during a given read clock cycle (Fairhurst teaches the existing scheduler/read-request infrastructure , including scheduler 540, read/dqueue request handling, request arbitration/reordering, and generation of reqd requests through the read launcher during scheduler operation ([0054] ] [0055]and Fig. 10). Shrivastava teaches timestamp information associated with control packet/control data processing ([0035]). It would have been obvious to use Shrivastava’s timestamp information in Fairhurst’s scheduler so the scheduler can compare arrival timing of queued CT and SAF control data and select the corresponding CTDQ or SAFDQ request during a read clock cycle, because timestamp comparison provides a deterministic way to choose between competing queued CT/SAF requests while preserving arrival-order fairness and supporting latency-aware scheduling)
Regarding claim 11, claim 11 is rejected based on the same rationale as claim 4;
Regarding claim 12, claim 12 is rejected based on the same rationale as claim 5;
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to TODD L. BARKER whose telephone number is (571) 270 0257. The Examiner can normally be reached on Monday through Friday, 7:30am to 5:00pm.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner's supervisor Vivek Srivastava can be reached on (571) 272 7304.
/TODD L BARKER/Primary Examiner, Art Unit 2449
