DETAILED ACTION
Claims 21-40 are pending. Claims 21, 28, 35 are pending. Claims 1-20 are cancelled.
Priority: 9/23/2015
Assignee: Oracle
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-20 of U.S. Patent No. 10,732,865. Although the claims at issue are not identical, they are not patentably distinct from each other because each limitation has obvious variants of each other.
Present(19/017,209)
Patent No. 10,732,865
An apparatus, comprising: an atomic transaction engine coupled to a processor and memory and configured to:
receive information describing an atomic transaction to be performed at an address of the memory, and responsive to the receiving:
write the information describing the atomic transaction into one or more storage locations accessible to the processor;
and issue an interrupt to the processor indicating that the atomic transaction should be executed by the processor.
6) a plurality of atomic transaction engine instances, each coupled via a respective memory interface to a respective one of the plurality of processor cores
11) and wherein to initiate the performance of the identified access operation by the second processor core, the second atomic transaction engine instance is configured to: write information about the identified access operation into one or more storage locations that are accessible to the second processor core;
11) and issue an interrupt to the second processor core indicating that the identified access operation should be executed by the second processor core.
wherein the information describing the atomic transaction is received from another processor responsive to determining that an operation to be executed by the other processor targets the memory.
6) wherein a first processor core of the plurality of processor cores comprises circuitry configured to: identify an access operation of an executing instruction that targets a location of data that is in the distributed shared random access memory
the processor configured to perform the atomic transaction responsive to receiving the interrupt.
12) wherein, in response to the interrupt, the second processor core is configured to perform the identified access operation
wherein the processor is further configured to write, into one or more other storage locations, response data for the performed atomic transaction,
and wherein the atomic transaction engine is further configured to send a response to the atomic transaction according to the response data.
11) the second atomic transaction engine instance is configured to: write information about the identified access operation into one or more storage locations that are accessible to the second processor core;
4) receiving, by the first atomic transaction engine instance from the second atomic transaction engine instance, a response frame comprising response data for the access operation; and in response to said receiving: returning, by the first atomic transaction engine instance, the response data to the first processor core;
wherein the memory controlled by the atomic transaction engine is a portion of a distributed shared memory controlled by a plurality of atomic transaction engines including the atomic transaction engine.
6) wherein each of the plurality of atomic transaction engine instances controls a respective portion of the distributed shared random access memory
wherein the atomic transaction targets a plurality of addresses of the distributed shared memory including the address of the memory controlled by the atomic transaction engine and one or more different addresses of respective memories controlled by other atomic transaction engines of the plurality of atomic transaction engines.
5) wherein the access operation targets multiple portions of the distributed shared random access memory, each associated with a different one of multiple ones of the plurality of processor cores
further comprising another processor configured to execute an instruction, wherein to execute the instruction the other processor is configured to:
identify that the instruction comprises an access targeting the address of the memory; and send the information to the atomic transaction engine instance responsive to the identifying.
6) identify an access operation of an executing instruction that targets a location of data that is in the distributed shared random access memory; and send, responsive to the identifying, parameters for the access operation via the respective memory interface to a first atomic transaction engine instance of the plurality of atomic transaction engine instances coupled to the first processor core;
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 21, 25-26, 28, 32, 33, 35, 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu(2004/0117562, “Wu”), and further in view of Chinya et al.(20110072234).
As per claim 21, Wu discloses:
A method, comprising:
receiving, at an atomic transaction engine from another atomic transaction engine, information describing an atomic transaction to be performed at an address of a memory controlled by the atomic transaction engine(Wu, [0050 -- As shown at 303, the memory controller may forward the request without the intervention of a processing device. The memory controller and the partner memory controller perform the write access]), and responsive to the receiving:
writing the information describing the atomic transaction into one or more storage locations accessible to a processor coupled to the atomic transaction engine(Wu, [0050 -- As shown at 303, the memory controller may forward the request without the intervention of a processing device. The memory controller and the partner memory controller perform the write access]);
Wu does not explicitly disclose the following, however Chinya discloses:
and issuing an interrupt to the processor indicating that the Chinya, [0026 -- The CPU thread performing the access may, in some embodiments stall pending completion of the remote access (and may switch to another thread). When the accelerator receives the PCIe.TM. transaction notifying of an access request from the CPU, the sequencer in the accelerator handles the request as a special interrupt event.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Chinya into the system of Wu for the benefit of providing architectural extensions to enhance a virtual memory management, so that special load/store transactions can be issued to address remote shared data and to enable the system to move memory pages to be closer to where they are accessed more frequently, thus allowing the processor to transparently use remote memory addresses to access shared data(Chinya, [0013]).
Claims 25 -26 are method/step claims that implement the apparatus of claims 32-33, respectively, and therefore the corresponding limitations are incorporated, as shown below.
As per claim 28, Wu discloses:
An apparatus, comprising:
an atomic transaction engine coupled to a processor and memory(Wu, [Fig. 1, 0065 -- Processing device 12A may execute firmware instructions 70 (e.g., stored in a ROM (Read Only Memory) 68 included in array controller 10A). The firmware 70 may be executable to initiate one or more read and write accesses to memory 16A]) and configured to:
receive information from another atomic transaction engine describing an atomic transaction to be performed at an address of the memory(Wu, [0050 -- As shown at 303, the memory controller may forward the request without the intervention of a processing device. The memory controller and the partner memory controller perform the write access]), and responsive to the receiving:
write the information describing the atomic transaction into one or more storage locations accessible to the processor(Wu, [0050 -- As shown at 303, the memory controller may forward the request without the intervention of a processing device. The memory controller and the partner memory controller perform the write access]);
Wu does not explicitly disclose the following, however Chinya discloses:
and issue an interrupt to the processor indicating that the Chinya, [0026 -- The CPU thread performing the access may, in some embodiments stall pending completion of the remote access (and may switch to another thread). When the accelerator receives the PCIe.TM. transaction notifying of an access request from the CPU, the sequencer in the accelerator handles the request as a special interrupt event.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Chinya into the system of Wu for the benefit of providing architectural extensions to enhance a virtual memory management, so that special load/store transactions can be issued to address remote shared data and to enable the system to move memory pages to be closer to where they are accessed more frequently, thus allowing the processor to transparently use remote memory addresses to access shared data(Chinya, [0013]).
As per claim 32, the rejection of claim 28 is incorporated, in addition, Wu discloses:
wherein the memory controlled by the atomic transaction engine is a portion of a distributed shared memory controlled by a plurality of atomic transaction engines including the atomic transaction engine(Wu, [0085 -- One array controller 10A may dynamically modify the base address and bound address for a shared memory region (e.g., for that array controller's reflected region) by modifying data stored in the metadata region. That array controller's memory controller 14A automatically broadcasts the modification via the memory-to-memory interconnect 18. In response to the modification being propagated to the remote array controllers, the remote array controllers may perform the metadata update, correspondingly increasing the size of their shared memory regions (e.g., by increasing the size of their partner-reflected regions if the local array controller increased the size of its reflected region).], [0052 -- This way, each access to the semaphore region completes atomically (i.e., the semaphore write does not complete locally unless it has completed remotely).]).
As per claim 33, the rejection of claim 32 is incorporated, in addition, Wu discloses:
wherein the atomic transaction targets a plurality of addresses of the distributed shared memory including the address of the memory controlled by the atomic transaction engine and one or more different addresses of respective memories controlled by other atomic transaction engines of the plurality of atomic transaction engines(Wu, [0085 -- One array controller 10A may dynamically modify the base address and bound address for a shared memory region (e.g., for that array controller's reflected region) by modifying data stored in the metadata region. That array controller's memory controller 14A automatically broadcasts the modification via the memory-to-memory interconnect 18. In response to the modification being propagated to the remote array controllers, the remote array controllers may perform the metadata update, correspondingly increasing the size of their shared memory regions (e.g., by increasing the size of their partner-reflected regions if the local array controller increased the size of its reflected region).], [0052 -- This way, each access to the semaphore region completes atomically (i.e., the semaphore write does not complete locally unless it has completed remotely).]).
As per claim 35, Wu discloses:
A system(Wu, [0034 -- FIG. 1 shows one embodiment of a distributed shared memory (DSM) system. Two nodes, node 10A and node 10B, are illustrated. In some embodiments, nodes 10A and 10B may each be configured as a storage controller (e.g., an array controller or a disk drive controller). Node 10A includes a processing device 12A, a memory controller 14A, and a memory 16A.]), comprising:
a plurality of atomic transaction engines respectively coupled to respective processors and respective memories(Wu, [0034 -- Two nodes, node 10A and node 10B, are illustrated. In some embodiments, nodes 10A and 10B may each be configured as a storage controller (e.g., an array controller or a disk drive controller). Node 10A includes a processing device 12A, a memory controller 14A, and a memory 16A.]), wherein the respective memories collectively implement a distributed shared memory, and wherein a local atomic transaction engine of the plurality of atomic transaction engines(Wu, [0040 -- In one embodiment, each shared region may occupy a set of contiguous physical memory addresses. Memory controller 14A may include mapping logic 34 in order to control each local memory access request targeting memory 16 dependent on which mapped region, if any, that local memory access request targets]) is configured to:
receive information from another atomic transaction engine of the plurality of atomic transaction engines describing an atomic transaction to be performed at an address of the memory(Wu, [0050 -- As shown at 303, the memory controller may forward the request without the intervention of a processing device. The memory controller and the partner memory controller perform the write access]), and responsive to the receiving:
write the information describing the atomic transaction into one or more storage locations accessible to a processor coupled to the local atomic transaction engine(Wu, [0050 -- As shown at 303, the memory controller may forward the request without the intervention of a processing device. The memory controller and the partner memory controller perform the write access]);
Wu does not explicitly disclose the following, however Chinya discloses:
and issue an interrupt to the processor indicating that the Chinya, [0026 -- The CPU thread performing the access may, in some embodiments stall pending completion of the remote access (and may switch to another thread). When the accelerator receives the PCIe.TM. transaction notifying of an access request from the CPU, the sequencer in the accelerator handles the request as a special interrupt event.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Chinya into the system of Wu for the benefit of providing architectural extensions to enhance a virtual memory management, so that special load/store transactions can be issued to address remote shared data and to enable the system to move memory pages to be closer to where they are accessed more frequently, thus allowing the processor to transparently use remote memory addresses to access shared data(Chinya, [0013]).
As per claim 39, the rejection of claim 35 is incorporated, in addition, Wu discloses:
wherein the atomic transaction targets a plurality of addresses of the distributed shared memory including the address of the memory controlled by the atomic transaction engine and one or more different addresses of respective memories controlled by other atomic transaction engines of the plurality of atomic transaction engines(Wu, [0085 -- One array controller 10A may dynamically modify the base address and bound address for a shared memory region (e.g., for that array controller's reflected region) by modifying data stored in the metadata region. That array controller's memory controller 14A automatically broadcasts the modification via the memory-to-memory interconnect 18. In response to the modification being propagated to the remote array controllers, the remote array controllers may perform the metadata update, correspondingly increasing the size of their shared memory regions (e.g., by increasing the size of their partner-reflected regions if the local array controller increased the size of its reflected region).], [0052 -- This way, each access to the semaphore region completes atomically (i.e., the semaphore write does not complete locally unless it has completed remotely).]);
and wherein another processor is configured to send the information describing an atomic transaction to the atomic transaction engine and the other atomic transaction engines(Wu, [0037 -- An access is initiated in response to an access request received by the memory controller 14, either directly from the processing device 12 or from another device via a local bus within the node (not shown). Access requests received in this way are described as being "local" (because the memory controller receives these access requests over an internal bus or interconnect within the node), while access requests received via the memory-to-memory interconnect 18 are described as being "remote."]).
Claim(s) 22-27, 29-34, 36-38, 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu(2004/0117562, “Wu”), in view of Chinya et al.(20110072234), and further in view of Duluk Jr. et al.(2014/0281299, “Duluk”).
Claims 22-27 are method/step claims that implement the apparatus of claims 29-34, respectively, and therefore the corresponding limitations are incorporated, as shown below.
As per claim 29, the rejection of claim 28 is incorporated, in addition, Wu, Chinya does not disclose the following, however Duluk discloses:
wherein the information describing the atomic transaction is received from another processor responsive to determining that an operation to be executed by the other processor targets the memory(Duluk, [0122 -- As shown, a method 500 begins at step 502, where the UVM driver 101 detects that the PPU 202 is accessing a CPU-owned memory page in system memory ]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Duluk into the system of Wu, Chinya for the benefit of efficient transition of memory pages between parallel processing unit and central processing unit is enabled in a multi-processor architecture. Parallel processing unit is enabled to access memory pages with high efficiency. (Duluk, 0127).
As per claim 30, the rejection of claim 28 is incorporated, in addition, Wu, Chinya does not explicitly disclose the following however Duluk discloses:
the processor configured to perform the atomic transaction responsive to receiving the interrupt(Duluk, [0122 -- At step 508, the CPU page table is updated to give the CPU read-only access to the memory page.], [0050 -- he page fault sequence generally maps the memory page associated with the requested virtual memory address or changes the types of accesses permitted (e.g., read access, write access, atomic access).]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Duluk into the system of Wu, Chinya for the benefit of efficient transition of memory pages between parallel processing unit and central processing unit is enabled in a multi-processor architecture. Parallel processing unit is enabled to access memory pages with high efficiency. (Duluk, 0127).
As per claim 31, the rejection of claim 30 is incorporated, in addition, in addition, Wu, Chinya does not explicitly disclose the following however Duluk discloses:
wherein the processor is further configured to write, into one or more other storage locations, response data for the performed atomic transaction, and wherein the atomic transaction engine is further configured to send a response to the atomic transaction according to the response data(Duluk, [0123 -- The PPU page table is also updated to map the memory page within the PPU memory 204. This step corresponds to the read duplicate state at time T=5, as shown in FIG. 4A. At step 522, the UVM driver 101 causes a CPU interrupt. At step 524, the memory page is unmapped in the CPU page table, and the memory page in the system memory 104 is identified as a free memory page]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Duluk into the system of Wu, Chinya for the benefit of efficient transition of memory pages between parallel processing unit and central processing unit is enabled in a multi-processor architecture. Parallel processing unit is enabled to access memory pages with high efficiency. (Duluk, 0127).
As per claim 34, the rejection of claim 28 is incorporated, in addition, in addition, Wu, Chinya does not explicitly disclose the following however Duluk discloses:
another processor configured to execute an instruction, wherein to execute the instruction the other processor is configured to: identify that the instruction comprises an access targeting the address of the memory and send the information to the atomic transaction engine instance responsive to the identifying(Duluk, [0122 -- As shown, a method 500 begins at step 502, where the UVM driver 101 detects that the PPU 202 is accessing a CPU-owned memory page in system memory 104 resulting in a page fault.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Duluk into the system of Wu, Chinya for the benefit of efficient transition of memory pages between parallel processing unit and central processing unit is enabled in a multi-processor architecture. Parallel processing unit is enabled to access memory pages with high efficiency. (Duluk, 0127).
As per claim 36, the rejection of claim 35 is incorporated, in addition, in addition, Wu does not explicitly disclose the following, however Duluk discloses:
wherein the information describing the atomic transaction is received from another processor responsive to determining that an operation to be executed by the other processor targets the memory(Duluk, [0122 -- As shown, a method 500 begins at step 502, where the UVM driver 101 detects that the PPU 202 is accessing a CPU-owned memory page in system memory ]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Duluk into the system of Wu for the benefit of efficient transition of memory pages between parallel processing unit and central processing unit is enabled in a multi-processor architecture. Parallel processing unit is enabled to access memory pages with high efficiency(Duluk, 0127).
As per claim 37, the rejection of claim 35 is incorporated, in addition, in addition, Wu does not explicitly disclose the following, however Duluk discloses:
the processor configured to perform the atomic transaction responsive to receiving the interrupt(Duluk, [0122 -- At step 508, the CPU page table is updated to give the CPU read-only access to the memory page.], [0050 -- he page fault sequence generally maps the memory page associated with the requested virtual memory address or changes the types of accesses permitted (e.g., read access, write access, atomic access).]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Duluk into the system of Wu for the benefit of efficient transition of memory pages between parallel processing unit and central processing unit is enabled in a multi-processor architecture. Parallel processing unit is enabled to access memory pages with high efficiency(Duluk, 0127).
As per claim 38, the rejection of claim 37 is incorporated, in addition, in addition, Wu does not explicitly disclose the following, however Duluk discloses:
wherein the processor is further configured to write, into one or more other storage locations, response data for the performed atomic transaction, and wherein the atomic transaction engine is further configured to send a response to the atomic transaction according to the response data(Duluk, [0123 -- The PPU page table is also updated to map the memory page within the PPU memory 204. This step corresponds to the read duplicate state at time T=5, as shown in FIG. 4A. At step 522, the UVM driver 101 causes a CPU interrupt. At step 524, the memory page is unmapped in the CPU page table, and the memory page in the system memory 104 is identified as a free memory page]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Duluk into the system of Wu for the benefit of efficient transition of memory pages between parallel processing unit and central processing unit is enabled in a multi-processor architecture. Parallel processing unit is enabled to access memory pages with high efficiency(Duluk, 0127).
As per claim 40, the rejection of claim 35 is incorporated, in addition, Wu does not explicitly disclose the following, however Duluk discloses:
another processor configured to execute an instruction, wherein to execute the instruction the other processor is configured to: identify that the instruction comprises an access targeting the address of the memory and send the information to the atomic transaction engine instance responsive to the identifying(Duluk, [0122 -- As shown, a method 500 begins at step 502, where the UVM driver 101 detects that the PPU 202 is accessing a CPU-owned memory page in system memory 104 resulting in a page fault.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Duluk into the system of Wu for the benefit of efficient transition of memory pages between parallel processing unit and central processing unit is enabled in a multi-processor architecture. Parallel processing unit is enabled to access memory pages with high efficiency(Duluk, 0127).
Response to Arguments
The Double Patenting Rejection is maintained.
The 35 USC 112(b) rejection is rescinded.
Applicant's arguments concerning the prior art rejections of claims 21-40, filed 4/29/2026 have been fully considered but they are not persuasive.
The applicant argues that claims 21-40 are allowable, based on the amendments applied to independent claims 21, 28 and 35. However the USPTO disagrees. Atleast for a significant portion of claim(s) 21, 28 and 35 the prior art of Wu, Figs. 1, 3 and 4A, as shown, applies. The claims are rejected on a combination of references not applied before based on the amendments. Regardless, the USPTO maintains all rejections.
Examiner’s Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fromm(2014/0068201) where processors in a compute node offload transactional memory accesses addressing shared memory to a transactional memory agent. The transactional memory agent typically resides near the processors in a particular compute node. The transactional memory agent acts as a proxy for those processors. A first benefit of the invention includes decoupling the processor from the direct effects of remote system failures. Other benefits of the invention includes freeing the processor from having to be aware of transactional memory semantics, and allowing the processor to address a memory space larger than the processor's native hardware addressing capabilities(Fromm, abstract).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARVIND TALUKDAR whose telephone number is (303)297-4475. The examiner can normally be reached M-F, 10 am-6pm EST.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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