Detailed Action
Status of Claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claims 1-20 are rejected,
This Action is Non-Final.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/10/2025 and 11/21/2025, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Harris et al.(US Patent Application Pub. No: 20130311745 A1) in view of Shanbhogue et al.(US Patent Application Pub. No: 20210311643 A1).
As pe claim 1,Harris teaches a memory module [Fig.2, the storage server 120.], comprising:
a substrate [Fig.2, an allocator subsystem 216.];
an allocator on the substrate [Fig.2, an allocator subsystem 216.];
a plurality of memory cluster packages on the substrate, the plurality of memory cluster packages being configured to be controlled by the allocator, wherein each of the plurality of memory cluster packages includes one or more memories and a memory controller [Paragraphs 0015;0053, …the storage system comprises an allocator subsystem and a metadata subsystem on one or more memory devices. The allocator subsystem may be configured to identify sequentially sensitive data having a position within a sequence, and allocate one or more contiguous disk blocks on the mass storage device based on the position of the sequentially sensitive data within the sequence.], and wherein the plurality of memory cluster packages includes a first memory cluster package and a second memory cluster package [Fig.2; Paragraphs 0053-0054, The memory 208 and server storage 212 may be any data storage device or devices capable of storing data.]; and
a plurality of serial communication lanes configured to transfer communications between the allocator and the plurality of memory cluster packages [Paragraph 0015, One or more client devices in communication with the allocator subsystem, the metadata subsystem, or both may write sequentially sensitive data to the one or more contiguous disk blocks allocated by the allocator subsystem.], wherein the plurality of serial communication lanes includes a first serial communication lane between the allocator and the first memory cluster package and a second serial communication lanes between the first memory cluster package and the second memory cluster package [Fig.2; Paragraphs 0053-0054, The memory 208 and server storage 212 may be any data storage device or devices capable of storing data.], wherein the first memory cluster package is configured to communicate with the allocator through the first serial communication lane using a serial communication protocol, and wherein the second memory cluster package is configured to communicate with the first memory cluster package through the second serial communication lane using the serial communication protocol [Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.].
Harris does not explicitly disclose the allocator being configured to communicate with an external device through a compute express link (CXL) interface;
a serial communication protocol.
Shanbhogue discloses the allocator being configured to communicate with an external device through a compute express link (CXL) interface [Fig.1; Paragraph 0016, System 100 includes a host computing system 102 coupled to a memory device 122 over a peripheral component interconnect express (PCIe) link 118 and a CXL link 120.];
a serial communication protocol [Fig.1, a CXL link 120.].
It would have been obvious one ordinary skill in the art before the effective filling, date of the claimed invention, to include Shanbhogue’s method for managing access to memory devices in a computing system into Harris’s system for recording and storing sequentially sensitive digital data for the benefit of enables managing access to the memory devices in the computing system in an effective manner (Shanbhogue, [0022]) to obtain the invention as specified in claim 1.
As per claim 2, Harris and Shanbhogue teach all the limitations of claim 1 above, where Harris and Shanbhogue teach, a memory module, wherein the first memory cluster package and the second memory cluster package are configured to communicate directly through the second serial communication lane [Harris , Paragraph 0015, One or more client devices in communication with the allocator subsystem, the metadata subsystem, or both may write sequentially sensitive data to the one or more contiguous disk blocks allocated by the allocator subsystem.], over a communication path that bypasses the allocator [Shanbhogue, Fig.1; Paragraph 0016, System 100 includes a host computing system 102 coupled to a memory device 122 over a peripheral component interconnect express (PCIe) link 118 and a CXL link 120.].
As per claim 3, Harris and Shanbhogue teach all the limitations of claim 2 above, where Harris and Shanbhogue teach, a memory module, wherein the second memory cluster package is configured to communicate [Harris , Paragraph 0015, One or more client devices in communication with the allocator subsystem, the metadata subsystem, or both may write sequentially sensitive data to the one or more contiguous disk blocks allocated by the allocator subsystem.], with the allocator through the first serial communication lane and the second serial communication lane using the serial communication protocol [Shanbhogue, Fig.1; Paragraph 0016, System 100 includes a host computing system 102 coupled to a memory device 122 over a peripheral component interconnect express (PCIe) link 118 and a CXL link 120.].
As per claim 4, Harris and Shanbhogue teach all the limitations of claim 2 above, where Harris and Shanbhogue teach, a memory module, wherein the plurality of serial communication lanes include a third serial communication lane between the allocator and the second memory cluster package [Shanbhogue, Fig.1; Paragraph 0016, System 100 includes a host computing system 102 coupled to a memory device 122 over a peripheral component interconnect express (PCIe) link 118 and a CXL link 120.], and
wherein the second memory cluster package is configured to communicate with the allocator through the third serial communication lane using the serial communication protocol [Harris , Paragraph 0015, One or more client devices in communication with the allocator subsystem, the metadata subsystem, or both may write sequentially sensitive data to the one or more contiguous disk blocks allocated by the allocator subsystem.].
As per claim 5, Harris and Shanbhogue teach all the limitations of claim 1 above, where Harris and Shanbhogue teach, a memory module, wherein the allocator includes:
a CXL communication circuit configured to support the CXL interface [Shanbhogue, Fig.1; Paragraph 0016, System 100 includes a host computing system 102 coupled to a memory device 122 over a peripheral component interconnect express (PCIe) link 118 and a CXL link 120.];
a cluster manager configured to control operations of the plurality of memory cluster packages [Harris, Paragraphs 0015;0053, …the storage system comprises an allocator subsystem and a metadata subsystem on one or more memory devices. The allocator subsystem may be configured to identify sequentially sensitive data having a position within a sequence, and allocate one or more contiguous disk blocks on the mass storage device based on the position of the sequentially sensitive data within the sequence.]; and
a plurality of serial communication circuits configured to support the serial communication protocol, the plurality of serial communication circuits including a first serial communication circuit, wherein the first serial communication circuit is configured to be communicatively connected to the first memory cluster package through the first serial communication lane [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.].
As per claim 6, Harris and Shanbhogue teach all the limitations of claim 5 above, where Harris and Shanbhogue teach, a memory module, wherein the plurality of serial communication circuits includes a second serial communication circuit [Shanbhogue, Fig.1; Paragraph 0016, System 100 includes a host computing system 102 coupled to a memory device 122 over a peripheral component interconnect express (PCIe) link 118 and a CXL link 120.],
wherein the plurality of serial communication lanes includes a third serial communication lane between the allocator and the second memory cluster package, and wherein the second serial communication circuit is configured to be communicatively connected to the second memory cluster package through the third serial communication lane [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.].
As per claim 7, Harris and Shanbhogue teach all the limitations of claim 5 above, where Harris teaches, a memory module, wherein at least one of the plurality of serial communication circuits, other than the first serial communication circuit, is configured to be disconnected from the plurality of serial communication lanes and the plurality of memory cluster packages [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.].
As per claim 8, Harris and Shanbhogue teach all the limitations of claim 1 above, where Harris and Shanbhogue teach, a memory module, wherein the first memory cluster package includes: a first memory controller [Shanbhogue, Fig.3,Paragraph 0066, … configuration 300 of memory controller (MC) 132 configuration space registers 302 and MMIO memory encryption engine (MEE) configuration and command registers 306 according to some embodiments.];
a plurality of first memories configured to be controlled by the first memory controller [Shanbhogue, Fig.3,Paragraph 0066, … configuration 300 of memory controller (MC) 132 configuration space registers 302 and MMIO memory encryption engine (MEE) configuration and command registers 306 according to some embodiments.]; and
a plurality of first serial communication circuits configured to support the serial communication protocol, the plurality of first serial communication circuits including a first-first serial communication circuit and a first-second serial communication circuit, wherein the first-first serial communication circuit is configured to be communicatively connected to the allocator through the first serial communication lane [Harris, Paragraphs 0015;0053, …the storage system comprises an allocator subsystem and a metadata subsystem on one or more memory devices. The allocator subsystem may be configured to identify sequentially sensitive data having a position within a sequence, and allocate one or more contiguous disk blocks on the mass storage device based on the position of the sequentially sensitive data within the sequence.], and wherein the first-second serial communication circuit is configured to be communicatively connected to the second memory cluster package through the second serial communication lane [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.].
As per claim 9, Harris and Shanbhogue teach all the limitations of claim 8 above, where Harris teaches, a memory module, wherein the first memory cluster package includes: a first cluster controller configured to control communication with the second memory cluster package [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.].
As per claim 10, Harris and Shanbhogue teach all the limitations of claim 8 above, where Harris and Shanbhogue teach, a memory module, wherein the first memory cluster package [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.], includes: a first processing unit (PU) configured to perform a computational operation on data stored in or read from the plurality of first memories [Shanbhogue, Paragraphs 0096-0097,Processing component 602 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), memory units, AI cores, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth.].
As per claim 11, Harris and Shanbhogue teach all the limitations of claim 8 above, where Harris and Shanbhogue teach, a memory module, wherein at least one of the plurality of first serial communication circuits, other than the first-first serial communication circuit and the first-second serial communication circuit [Shanbhogue, Fig.1; Paragraph 0016, System 100 includes a host computing system 102 coupled to a memory device 122 over a peripheral component interconnect express (PCIe) link 118 and a CXL link 120.], is configured to be disconnected from the plurality of serial communication lanes, the allocator, and memory cluster packages, other than the first memory cluster package, among the plurality of memory cluster packages [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.].
As per claim 12, Harris and Shanbhogue teach all the limitations of claim 8 above, where Harris and Shanbhogue teach, a memory module, wherein the second memory cluster package includes: a second memory controller [Shanbhogue, Fig.3,Paragraph 0066, … configuration 300 of memory controller (MC) 132 configuration space registers 302 and MMIO memory encryption engine (MEE) configuration and command registers 306 according to some embodiments.];
a plurality of second memories configured to be controlled by the second memory controller [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.]; and
a plurality of second serial communication circuits configured to support the serial communication protocol, the plurality of second serial communication circuits including a second- first serial communication circuit, and wherein the second-first serial communication circuit is configured to be communicatively connected to the first memory cluster package through the second serial communication lane [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.].
As per claim 13, Harris and Shanbhogue teach all the limitations of claim 12 above, where Harris and Shanbhogue teach, a memory module, wherein the plurality of second serial communication circuits includes a second-second serial communication circuit, and wherein the plurality of serial communication lanes includes a third serial communication lane between the allocator and the second memory cluster package [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.], and
wherein the second-second serial communication circuit is configured to be communicatively connected to the allocator through the third serial communication lane [Shanbhogue, Fig.1; Paragraph 0016, System 100 includes a host computing system 102 coupled to a memory device 122 over a peripheral component interconnect express (PCIe) link 118 and a CXL link 120.].
As per claim 14, Harris and Shanbhogue teach all the limitations of claim 12 above, where Harris and Shanbhogue teach, a memory module, wherein at least one of the plurality of second serial communication circuits [Shanbhogue, Fig.1; Paragraph 0016, System 100 includes a host computing system 102 coupled to a memory device 122 over a peripheral component interconnect express (PCIe) link 118 and a CXL link 120.], other than the second-first serial communication circuit, is configured to be disconnected from the plurality of serial communication lanes, the allocator, and memory cluster packages, other than the second memory cluster package, among the plurality of memory cluster packages [Harris, Paragraphs 0054-0055, The allocator subsystem 216 and the metadata subsystem 220 of one or more embodiments may utilize the memory 208, server storage 212, and processor 204 to store, process, retrieve, and communicate data required for these subsystems to operate. In addition, the allocator subsystem 216 and the metadata subsystem 220 may execute on different servers in one or more embodiments.].
As per claims 15-19, claims 15-19 are rejected in accordance to the same rational and reasoning as the above claims 1-5 and 10-14 above, wherein claims 15-19 are the system claims for the device of claims 1-5 and 10-14.
As per claim 20, claim 20 is rejected in accordance to the same rational and reasoning as the above claims 1-5,8 and 10-14 above, wherein claim 20 is the device claim for the device of claims 1-5,8 and 10-14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the
level of skill in the applicant’s art and those arts considered reasonably pertinent to
applicant’s disclosure. See MPEP 707.05(c).
References Considered Pertinent but not relied upon
FRANCIS et al. (US Patent Application Pub. No: 20230117047 A1) teaches a method of managing computational and power resources in a datacenter includes receiving an application request at an allocator to execute a requested application, identifying an idle computing device in the datacenter, obtaining an efficiency parameter for the idle computing device, obtaining a normalized power demand of the requested application, and determining a device power demand for the requested application on the idle computing device based at least partially on the efficiency parameter and a normalized power demand for the requested application.
LEE et al. (US Patent Application Pub. No: 20160036608 A1) teaches a first communication device is provided. LEE discloses the first communication device modulates data to generate a first data symbol; and the first communication device generates a first signal by using a first signal waveform allocated among a plurality of mutually orthogonal signal waveforms and the first data symbol. LEE suggests the first communication device outputs the first signal to a serial line connected to a second communication device.
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/GETENTE A YIMER/Primary Examiner, Art Unit 2181
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