DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 09/25/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 01/10/2025. These drawings are acceptable.
Specification
The abstract of the disclosure does not commence on a separate sheet in accordance with 37 CFR 1.52(b)(4) and 1.72(b). A new abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text.
Claim Objections
Claims 1, 11, 4, 14, and 20 are objected to because of the following informalities:
Claims 1, 11, and 20, the phrase “an target” should be replaced with “a target”.
Claim 4 and 14, the phrase “an voltage outer loop and an current inner loop” should be replaced with “a voltage outer loop and a current inner loop”
As submitted, the limitation of claim 20 “acquiring a three-phase target output voltage of the converter according to the target output reference voltage on the first axis and the target output reference voltage on the second axis” is separate from the claim set submitted and is included on the Abstract page. For the purpose of examination, the limitation will be included with claim 20, however a replacement claim set is required with the complete claim separate from the Abstract page.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the “computer readable storage medium” of claim 20 encompasses signals per se. The specification states that a “one or more storage media 330 (e.g. one or more mass storage devices) that store applications 342 or data 344. Here, the memory 332 and the storage medium 330 may be transient or persistent storage” which clearly includes propagating electromagnetic waves. The further recitation of “implements operations” in claim 20 only serves to limit the content carried by the electromagnetic waves. As understood in light of the specification, the broadest reasonable interpretation of claim 20 encompasses signals which are not within one of the four statutory categories of invention. See MPEP 2106.03(I). It is suggested that claim 20 be amended to recite a “non-transitory” computer readable storage medium to overcome this rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 7, 11-13, 15, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ebrahimzadehveshareh et al. (US 12176842 B2), hereinafter Ebrahimzadehveshareh.
Regarding claims 1 and 11, Ebrahimzadehveshareh discloses a converter (col 1 lines 29-30 “power converters with grid-forming properties”; fig. 2A, power converter 202), comprising: a memory, configured to store a computer program (claim 1, “control system, comprising a memory communicatively coupled to one or more processors”); and a processor, configured to execute the computer program (claim 1, “one or more processors configured to perform an operation”; implicit that a processor executes a computer program) to perform operations of a current limiting control method for a grid-forming converter (col 6 lines 52-54 “current limiting method implemented in a virtual synchronous generator”), the current limiting control method comprising: acquiring a three-phase output reference voltage of a converter (col 5 lines 29-31” The power system 200 is principally illustrated and therefore does not explicitly reveal that the system may be a three phase system”; internal voltage magnitude reference Vqref used to generate modified voltage reference of the converter Vdq_m), wherein an output end of the converter is connected to a power grid (fig 2A, output of converter 204 connected to High voltage power grid 220); performing a transformation to obtain an output reference voltage on a first axis and an output reference voltage on a second axis in a preset two-phase coordinate system corresponding to the three-phase output reference voltage (fig 4, Vdref and Vqref are the components of Vdqref in DQ transformation; col 11 lines 50-52); performing virtual impedance current limiting adjustment (col 6 lines 59-62 “current limiting method is to insert a virtual impedance Zvir between the output of the line side converter 204 and the grid or the grid connection such as the transformer 208”) on the output reference voltage on the first axis and/or the output reference voltage on the second axis by using a preset maximum output current limit value of the converter, to obtain an target output reference voltage on the first axis and/or an target output reference voltage on the second axis in the preset two- phase coordinate system, wherein the preset maximum output current limit value comprises: an output current limit value on the second axis corresponding to the output reference voltage on the first axis, and/or an output current limit value on the first axis corresponding to the output reference voltage on the second axis (col 11 lines 10-12 “virtual voltage ΔVdq is combined, here subtracted, with the voltage reference Vdqref to generate the modified voltage reference Vdq_m”; see col 10 lines 50-56 equation for ΔVdq; col 7 line 14-18 Imax overcurrent threshold value Imax; col 9 lines 55- 65 virtual impedance Zvir is determined based on the current difference or current error Ierr, i.e. the difference between the current magnitude Im1 or Im2 and the overcurrent threshold value Imax); and acquiring a three-phase target output voltage (fig 4, Vabc input to PWM 265; col 11 lines 40-52 “Vabc”) according to the target output reference voltage on the first axis and the target output reference voltage on the second axis (fig 4, Vabc based on Vdref and Vqref in DQ form).
Regarding claims 2 and 12, Ebrahimzadehveshareh discloses the converter/method of claim 1/11, wherein the converter is an inverter (fig 2A, DC/AC inverter in converter 202), and the three-phase output reference voltage is a three-phase reference voltage of a Virtual Synchronous Generator (VSG) (abstract “determine a voltage reference for controlling the line side converter to generate the desired reactive power based on the virtual synchronous machine rotational speed or angle, the virtual voltage and the voltage magnitude reference”).
Regarding claims 3 and 13, Ebrahimzadehveshareh discloses the converter/method of claim 1/11, wherein the preset two-phase coordinate system is a dq rotary coordinate system, the first axis corresponds to an active power and the second axis corresponds to a reactive power (col 9 lines 7-12 “two-axis frame DQ which rotates according to the angle ENSM”; col 6 lines 25-27 “The modulation voltage reference signal controls the active and reactive power Pgrid and Qgrid”).
Regarding claims 5 and 15, Ebrahimzadehveshareh discloses the converter/method of claim 1/11, wherein the processor is further configured to execute the computer program to perform the operation of performing the virtual impedance current limiting adjustment on the output reference voltage on the first axis and/or the output reference voltage on the second axis by using the preset maximum output current limit value of the converter, to obtain the target output reference voltage on the first axis and/or the target output reference voltage on the second axis in the preset two-phase coordinate system (see claims 1-2 rejections above for exact limitations mapped to prior art) by: determining, through a proportional integral control link (fig 4, PI controller with output Rvir), a voltage adjustment value on the first axis according to the output current limit value on the second axis and an output current on the second axis (col 9 line 66- col 10 line 33; fig 4, equations for voltage ΔVdq over the virtual impedance Zvir is ΔVd=Rvir_lim×Id−Xvir×Iq and ΔVq=Rvir_lim×Iq+Xvir×Id; the equations are for cross-coupled virtual impedance); and adjusting the output reference voltage on the first axis by using the voltage adjustment value on the first axis, to obtain the target output reference voltage on the first axis (adjustment values ΔVd and ΔVq are subtracted from the initial references Vdref and Vqref at the summing junction to get Vdq_m before going to Vabc at the imput to PWM generator to drive the converter 204); and/or determining, through the proportional integral control link, a voltage adjustment value on the second axis according to the output current limit value on the first axis and an output current on the first axis; and adjusting the output reference voltage on the second axis by using the voltage adjustment value on the second axis, to obtain the target output reference voltage on the second axis (col 9 line 66- col 10 line 33; fig 4, equations for voltage ΔVdq over the virtual impedance Zvir is ΔVd=Rvir_lim×Id−Xvir×Iq and ΔVq=Rvir_lim×Iq+Xvir×Id; the equations are for cross-coupled virtual impedance; adjustment values ΔVd and ΔVq are subtracted from the initial references Vdref and Vqref at the summing junction to get Vdq_m before going to Vabc at the input to PWM generator to drive the converter 204); wherein the output current on the second axis and the output current on the first axis are obtained by transforming a three-phase output current of the converter into the preset two- phase coordinate system (fig 4, three phase Igrid input to abc/DQ block, output Idq, Id, and Iq), the output current on the first axis is an active current, and the output current on the second axis is a reactive current (fig 4, Id, and Iq represent active current and reactive current of the DQ transformation).
Regarding claim 7/17, Ebrahimzadehveshareh discloses the converter/method of claim 5/15, wherein when performing the virtual impedance current limiting adjustment on the output reference voltage on the first axis by using the preset maximum output current limit value of the converter, to obtain the target output reference voltage on the first axis in the preset two-phase coordinate system (see claims 5/15 rejections above for exact limitations mapped to prior art) the processor is further configured to execute the computer program to perform operations of: determining a voltage condition of the power grid according to a voltage drop value of a virtual impedance (col 6 lines 53-55 “a current limiting method implemented in a virtual synchronous generator which is activated during abnormal grid conditions and overcurrent situations”; virtual impedance elements Xvir and Rvir_lim are multiplied by the grid currents Id, Iq to compute a dynamic voltage drop vector ΔVd and ΔVq utilizing equations ΔVd=Rvir_lim×Id−Xvir×Iq and ΔVq=Rvir_lim×Iq+Xvir×Id. These voltage drops ΔVdq are subtracted from the core Virtual Synchronous Machine VSM nominal voltage references Vdref, Vqref to drop the internal modulation voltage output Vabc via the DQ/abc block fed into the Pulse Width Modulator PWM to bring the converter output current back under the threshold boundary), wherein the output current on the second axis is taken as a target output current (fig 4, output Idq, Iq), the output current limit value on the second axis is taken as a preset maximum reactive current limit value (fig 4, the current magnitude calculation block Im1= square root of the squares of the current components Id, Iq, second axis acting as the reactive current Iq is capped by the upper threshold block Imax, functioning as the preset maximum reactive current limit during fault conditions), and the voltage drop value of the virtual impedance is the voltage adjustment value on the first axis (fig 4, ΔVdq output is subtracted directly from the reference values Vdqref of Vqref and Vqref to generate the modified voltage adjustment commands Vdq_m); and reducing, if the voltage condition is that a fault occurs, a given value of an active power of the converter to a preset power value (col 12 lines 48-58 “magnitude and angle difference between Vabc and Ugrid are decreased, the large values of the grid current Igrid or the grid current magnitude is prevented”).
Regarding claim 20, Ebrahimzadehveshareh discloses a non-transitory computer-readable storage medium having stored thereon a computer program that, when executed by a processor (claim 1, “a memory communicatively coupled to one or more processors; the one or more processors configured to perform an operation”), implements operations of a current limiting control method for a grid- forming converter (see claims 1/11 rejections above for exact limitations mapped to prior art).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ebrahimzadehveshareh et al. (US 12176842 B2) as applied to claims 1 and 11 above, and further in view of Shao et al. (CN 110233495 A) hereinafter Shao.
Regarding claims 4 and 14, Ebrahimzadehveshareh discloses the converter/method of claim 1/11, wherein the processor is further configured to execute the computer program to perform the operation (claim 1 “the one or more processors configured to perform an operation”) of acquiring the three-phase target output voltage of the converter according to the target output reference voltage on the first axis and the target output reference voltage on the second axis (fig 4, Vabc input to PWM 265; col 11 lines 40-52 “Vabc”;Vabc based on Vdref and Vqref in DQ form).
Ebrahimzadehveshareh fails to disclose obtaining, through a double closed-loop control of an voltage outer loop and an current inner loop, a target output voltage on the first axis and a target output voltage on the second axis in the preset two-phase coordinate system according to the target output reference voltage on the first axis and the target output reference voltage on the second axis; and transforming the target output voltage on the first axis and the target output voltage on the second axis to the three-phase target output voltage.
Shao discloses grid inverter control with virtual synchronous output reference voltage EVSG and virtual impedance adjustment to adjust the internal parameter of the voltage loop and current loop. Shao discloses obtaining, through a double closed-loop control of an voltage outer loop and an current inner loop (fig 6, outer voltage loops including references V* d and V* q and inner current including output current of the voltage loop references I* d, I* q), a target output voltage on the first axis and a target output voltage on the second axis in the preset two-phase coordinate system according to the target output reference voltage on the first axis and the target output reference voltage on the second axis (fig 6, see DQ transformation blocks); and transforming the target output voltage on the first axis and the target output voltage on the second axis to the three-phase target output voltage (fig 6, target voltages from the dq axis are converted into the two-phase stationary frame using the grid phase angle θg provided by the PLL. SVPWM processes θg to output the final three-phase target voltages Vma, Vmb, Vmc).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ebrahimzadehveshareh and incorporate the use of double outer voltage and inner current control loops as taught by Shao. The advantage of this design is for dynamic response and stability in handling rapid electrical variations and transient changes at a much higher sampling frequency. Because it reacts quickly to disturbances, it isolates the outer voltage loop from sudden grid or load fluctuations, leading to excellent overall stability.
Allowable Subject Matter
Claims 6, 8-10, 16, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 6 and 16, Ebrahimzadehveshareh discloses the converter/method of claim 5/15, wherein the processor is further configured to execute the computer program to perform the operation of determining, through the proportional integral control link (fig 4, PI controller), the voltage adjustment value on the first axis according to the output current limit value on the second axis (fig 4, PI controller output Rvir to limiter to generate Rvir_lim to obtain voltage adjustments utilizing equations for ΔVd and ΔVq)
Ebrahimzadehveshareh fails to disclose the output current on the second axis by calculating the voltage adjustment value on the first axis through
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; wherein Uvd denotes the voltage adjustment value on the first axis, iqLim denotes the output current limit value on the second axis, iq denotes the output current on the second axis, ki denotes an integral coefficient, kp denotes a proportional coefficient, and s denotes an operator variable of a Laplace transformation; iqLim is positive if iq > 0, and iqLim is negative if iq<0; and adjusting, if iq > 0, the voltage adjustment value on the first axis to a first threshold when the voltage adjustment value on the first axis is greater than the first threshold; and adjusting, if iq<0, the voltage adjustment value on the first axis to a second threshold when the voltage adjustment value on the first axis is less than the second threshold; wherein determining, through the proportional integral control link, the voltage adjustment value on the second axis according to the output current limit value on the first axis and the output current on the first axis comprises: calculating the voltage adjustment value on the second axis through
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; wherein Uvq denotes the voltage adjustment value on the second axis, idLim denotes the output current limit value on the first axis, and id denotes the output current on the first axis; idLemis positive if id > 0, and idLim is negative if id < 0; and adjusting, if id>0, the voltage adjustment value on the second axis to a third threshold when the voltage adjustment value on the second axis is greater than the third threshold; and adjusting, if id<0 , the voltage adjustment value on the second axis to a fourth threshold when the voltage adjustment value on the second axis is less than the fourth threshold.
Ebrahimzadehveshareh has been found to be the closest prior art of record.
However, none of the prior art, taken singly or in combination, teach “the output current on the second axis by calculating the voltage adjustment value on the first axis through
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; wherein Uvd denotes the voltage adjustment value on the first axis, iqLim denotes the output current limit value on the second axis, iq denotes the output current on the second axis, ki denotes an integral coefficient, kp denotes a proportional coefficient, and s denotes an operator variable of a Laplace transformation; iqLim is positive if iq > 0, and iqLim is negative if iq<0; and adjusting, if iq > 0, the voltage adjustment value on the first axis to a first threshold when the voltage adjustment value on the first axis is greater than the first threshold; and adjusting, if iq<0, the voltage adjustment value on the first axis to a second threshold when the voltage adjustment value on the first axis is less than the second threshold; wherein determining, through the proportional integral control link, the voltage adjustment value on the second axis according to the output current limit value on the first axis and the output current on the first axis comprises: calculating the voltage adjustment value on the second axis through
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; wherein Uvq denotes the voltage adjustment value on the second axis, idLim denotes the output current limit value on the first axis, and id denotes the output current on the first axis; idLemis positive if id > 0, and idLim is negative if id < 0; and adjusting, if id>0, the voltage adjustment value on the second axis to a third threshold when the voltage adjustment value on the second axis is greater than the third threshold; and adjusting, if id<0 , the voltage adjustment value on the second axis to a fourth threshold when the voltage adjustment value on the second axis is less than the fourth threshold”.
Claims 8-10 and 18-19 are indicated as allowable for their dependency on claims 6 and 16.
Conclusion
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838 /THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
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