DETAILED ACTION
Response to Amendment
1. Applicant’s amendment filed on 10/02/26 has been received and entered in the case. The amendments to the claims do not distinguish patentably over the previously applied Kerr et al reference (USP 10,320,379), for the reasons set forth below.
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 21, 22, 24, 26, 27, 29-38, 40, 42 and 43 are rejected under 35 U.S.C. 103 as being unpatentable over Kerr et al (USP 10,320,379) in view of Kelly et al (USP 7,613,442).
As to claim 21, Kerr et al discloses, in figure 2,
a switch circuit comprising:
a first terminal (the terminal at which signal RF1 is applied);
a second terminal (the terminal from which signal RF2 is output);
a first transistor switch stack comprising:
a first plurality of transistors (transistors Q1 through QN) coupled between the first terminal and the second terminal, wherein each transistor is coupled to at least one other transistor of the first plurality of transistors;
a first plurality of resistors (resistors RG), wherein each resistor of the first plurality of resistors is coupled between gates of a respective pair of transistors among the first plurality of transistors;
a first capacitor (capacitor CG1) coupled between the first terminal and a first resistor of the first plurality of resistors;
a second plurality of resistors (resistors RB), wherein each resistor of the second plurality of resistors is coupled between bodies of the respective pair of resistors among the first plurality of transistors; and
a second capacitor (capacitor CB1) coupled between the first terminal and a first resistor of the second plurality of resistors.
Not disclosed by Kerr et al is the claimed third terminal configured to be coupled to ground and the second transistor switch stack comprising the limitations recited on the last eight lines of claim 21.
Kelly et al discloses, in figure 3, a single pole double throw (SPDT) switch circuit which includes first through fourth transistor switch stacks, two of which are series switch stacks and the other two of which are shunt switch stacks, wherein all four switch stacks comprise the same structure, i.e., three series connected transistors, each with a respective gate resistor and each of which is activated or deactivated in response to a common control signal SW or SW_.
It would have been obvious to one of ordinary skill in the art to combine the above-noted teachings in Kerr et al and Kelly et al such that first through fourth switch stacks, each formed as shown in Kerr et al’s figure 2, are arranged in a SPDT switch circuit, i.e., a first Kerr et al figure 2 switch stack between an RF port 1 and RF COMMON, a second Kerr et al figure 2 switch stack between RF COMMON and an RF port 2, a third Kerr et al figure 2 switch stack between RF port 1 and ground, and a fourth Kerr et al figure 2 switch stack between RF port 2 and ground, wherein all four of such Kerr et al figure 2 switch stacks comprise the same structure, i.e., the structure shown in figure 2 of Kerr et al. The motivation for combining the teachings of Kerr et al and Kelly et al is to provide the benefits associated with using a single pole double throw (SPDT) switch circuit, i.e., the capability of using an antenna for transmitting and receiving two different radio frequency signals in, e.g., a smart phone. Applicant should note that when such a combination of Kerr et al and Kelly et al is made, there will be a shunt switch stack between the above-noted first terminal in figure 2 of Kerr et al and ground, where ground is the claimed third terminal recited on line 4 of claim 21, and such a shunt switch stack will comprise a second plurality of transistors (Q1 through QN) coupled between the first terminal and the third terminal, each transistor of the shunt switch stack will be coupled to at least one other transistor of the second plurality of transistors, there will be a third plurality of resistors (RG) coupled between gates of the respective pair of transistors among the second plurality of transistors, and there will be a third capacitor (capacitor CG1) coupled between the first terminal and a first resistor of the third plurality of resistors.
As to claim 22, the claimed first transistor is transistor Q1, the claimed second transistor is transistor QN, the claimed second resistor is resistor RG1, and the claimed third resistor is resistor RB1.
As to claim 24, note that the first plurality of resistors form a gate bias resistor ladder having a first end (the first end is at the terminal between RG1 and the leftmost resistor RG) coupled to the second resistor and a second end (the second end is at the terminal between any pair of resistors RG other than the leftmost resistor RG in Kerr et al’s figure 2) configured to receive a gate bias voltage (note that the gate bias voltage at terminal 22 in figure 2 of Kerr et al passes through to the final resistor RGN, and therefore the claimed second end will receive the gate bias voltage GATE CONTROL shown in figure 2 of Kerr et al. Alternatively, the claimed second end can be read on the terminal which receives the GATE CONTROL bias voltage, when this bias voltage is applied to the midpoint of the gate bias resistor ladder for the case where the Kerr et al figure 2 switch circuit is modified as shown in figure 3 of this reference, i.e., such that the bias voltage is applied to the midpoint of the resistors RG. Note that under either of these two interpretations, the second plurality of resistors (resistors RB) will form a body charge control resistor ladder having a first end coupled to the third resistor and a second end configured to receive the body bias voltage BODY CONTROL shown in figure 2 of Kerr et al, using the same analysis as noted above for the first and second ends of the gate bias resistor ladder.
As to claim 26, the claimed one or more transistors are transistors Q2 through Q7.
As to claim 27, note that resistors RG and RB in Kerr et al’s figure 2 are coupled as recited in this claim.
As to claim 29, the claimed fourth plurality of resistors are resistors RSD shown in Kerr et al’s figure 2, note that these resistors form a drain-source resistor ladder having a first end (the node between the two leftmost resistors RSD) coupled to the above-noted first terminal and a second end (the node between the two rightmost resistors RSD) coupled to the above-noted second terminal.
As to claims 30-38 and 40, the limitations of these method claims are rejected using the same reasoning and analysis as set forth above in the rejections of claims 21, 22, 24, 26, 27 and 29 (as to the limitation that at least one transistor of the first plurality of transistors is a positive-logic field-effect transistor, note that transistors Q1 through QN shown in figure 2 of Kerr et al can each be interpreted as being a positive-logic
field-effect transistor because each is an NMOS field-effect transistor which turns on in response to logic high (positive) logic level at its respective gate terminal.
As to claim 42, note that in Kerr et al as modified by Kelly et al above, the first transistor switch stack will be in a series configuration between the first and second terminals, the second transistor switch stack will be coupled in a shunt configuration between the first and third terminals, and any two of the resistors RG will be connected together at the node which receives the first gate bias voltage GATE CONTROL, i.e., as noted above, this gate bias voltage will be received by all of the gate resistors RG in figure 2 of Kerr et al.
As to claim 43, note that in Kerr et al as modified by Kelly et al above, the third plurality of resistors form a gate bias resistor ladder having an end (the end of the gate bias resistor ladder which receives bias voltage GATE CONTROL in figure 2 of Kerr et al) configured to receive a second gate bias voltage (the GATE CONTROL bias voltage which is received by the shunt switch stack).
3. Claims 28 and 41 are rejected under 35 U.S.C. 103 as being unpatentable over Kerr et al, supra, in view of Kelly et al, supra, as applied to claim 21 above, and further in view of Bakalski et al (USPAP 2016/0329891).
As to claim 28, as noted above in the rejection of claim 29, Kerr et al discloses a fourth plurality of resistors (resistors RSD), wherein each resistor is coupled between the drain and a source of a respective transistor of transistors Q1 through QN, wherein the resistors RSD form a drain-source resistor ladder, and note further that Kerr et al’s figure 2 shows that the above-noted first terminal is configured to be coupled to a radio frequency voltage source (the radio frequency voltage source which outputs radio frequency signal RF1).
Not disclosed by Kerr et al in figure 2 is that the drain-source resistor ladder has a first end configured to receive a drain-source bias voltage.
Bakalski et al discloses, in figure 3a, a plurality of resistors RDS, each of which is coupled between a drain and a source of a respective transistor of a first plurality of transistors, wherein the plurality of resistors form a drain-source resistor ladder having a first end (the node between resistors RDS and RGND) configured to receive a drain-source bias voltage (ground potential).
It would have been obvious to one of ordinary skill in the art to modify figure 2 of Kerr et al using the above-noted teaching in Bakalski et al such that a drain-source bias voltage is received at a first end of Kerr et al’s drain-source resistor ladder, the motivation for such a modification to figure 2 of Kerr et al is to provide a bias voltage to transistors Q1 through QN when the switch stack is turned off, as taught by Bakalski et al, note what is indicated on the last five lines of paragraph [0033] of this reference.
As to claim 41, the claimed first end, as noted above in the rejection of claim 28, is at the node between resistors RDS and RGND in Bakalski et al’s figure 3a and the claimed first node is the node which connects the source/drain of transistor M0 to the source/drain of the transistor immediately below transistor M0. Note also that the claimed second end of the claimed drain-source resistor ladder is at the top terminal of the resistor RDS of Bakalski et al’s drain-source resistor ladder, note that this terminal is coupled to the source/drain of transistor M2, and the claimed second node is at the source/drain terminal of transistor M2 which is coupled to the source/drain of transistor Mn in figure 3a of Bakalski et al. Note also that when figure 2 of Kerr et al is modified using the above-noted teachings in Bakalski et al, the drain-source resistor ladder of Kerr et al’s figure 2 will be coupled to ground potential at a first end of the drain-source resistor ladder at a first node, and a second end of Kerr et al’s drain-source resistor ladder will be coupled to a second node.
4. Claim 44 is rejected under 35 U.S.C. 103 as being unpatentable over Kerr et al, supra, in view of Kelly et al, supra, as applied to claim 24 above, and further in view of Kawakyu et al (USP 6,978,122).
Kerr et al discloses a fourth resistor, i.e., the resistor RGC1 shown in figure 3 of this reference, and as noted above, the gate bias voltage GATE CONTROL can obviously be applied to the midpoint of the gate resistor ladder formed by resistors RG in view of Kerr et al’s figure 3, note that such a fourth resistor is connected to a first node (node 22 shown in Kerr et al’s figure 3) and to the above-noted second end of the gate bias resistor ladder formed by resistors RG, and note also that node 22 is configured to receive the gate bias voltage GATE CONTROL.
Not disclosed by Kerr et al in figure 3 is the claimed fourth capacitor connected to the first node 22, wherein the fourth capacitor is configured to be coupled to ground.
Kawakyu et al discloses, in figure 2, a switch circuit for transmitting a radio frequency signal wherein the control voltage Vcon used for activating or deactivating the field-effect switches is coupled to a first node, and wherein a capacitor 109 is coupled between the first node and ground.
It would have been obvious to one of ordinary skill in the art to combine the above-noted teachings in Kerr et al’s figure 2 and Kawakyu et al’s figure 2 such that a fourth capacitor is coupled between Kerr et al’s gate bias node 22 and ground, as taught by Kawakyu et al, the motivation for such a modification to Kerr et al’s figure 2 is to provide the well-known benefit obtained by using such a capacitor, i.e., to provide filtering of any noise that might be present at bias node 22.
Action is Final
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2836 October 9, 2026
