DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 9 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 15 and 9, respectively, of U.S. Patent No. 12,204,792. Although the claims at issue are not identical, they are not patentably distinct from each other because Claims 15 and 9, respectively, of U.S. Patent No. 12,204,792 recite all of the elements of Claims 9 and 15 of the instant application, wherein the claims of U.S. Patent No. 12,204,792 recite additional narrowing features.
Instant – 19/017,337
US Patent – 12,204,792
Claim 9: A memory system, comprising:
one or more memory devices, wherein at least one memory device of the one or more memory devices comprises
--a plurality of clocks; and
--one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
--receive one or more commands while operating in a first mode;
--calculate, in response to receiving the one or more commands and after transitioning from the first mode to a second mode, a throughput of the one or more commands; and
--adjust a rate of each clock of the plurality of clocks in accordance with the calculated throughput of the one or more commands.
Claim 15: An apparatus, comprising:
a memory system comprising (+Fig. 1: Memory System 110 comprising Memory Devices 130)
--a plurality of clocks, each of the plurality of clocks associated with a respective subcomponent of the memory system; and
--a controller coupled with the memory system, the controller configured to:
--store at least one command of a plurality of received commands in a queue while operating the memory system in a first mode;
--transition the memory system from operating in the first mode to a second mode to determine a throughput of the plurality of received command.... determine, while operating in the second mode, the throughput of the plurality of received commands...;
--adjust a rate of at least one of the plurality of clocks to a second rate lower than the maximum rate based at least in part on determining the throughput of the plurality of received commands.
Claim 15: The memory system of claim 9, wherein the first mode comprises an idle mode of the memory system and the second mode comprises an analysis mode of the memory system.
Claim 9: ... store at least one command of a plurality of received commands in a queue while the memory system is operating in an idle mode... transition the memory system from the idle mode to an analysis mode to determine a throughput... (See also the Specification Col. 13 ll. 20-38).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4-5, 8-9, 13-16 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong (US PGPUB 2017/0277446) in view of Ware et al. (US PGPUB 2013/0083611).
With regard to Claim 2, Cheong teaches a memory system, comprising:
one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to ([0031] “The storage device 20 may include ... a memory controller 200... and a nonvolatile memory 400.”):
receive, while operating in a first mode, one or more commands associated with a first pattern ([0037] “the host interface 220 may receive data, DATA, or a command CMD from the host 10.” [0038] “the host interface 220 may generate the operation information OP or the pattern information PT on the basis of the data.” [0083] “The pattern detector 222 may generate pattern information PT of an operation to be performed by the storage device 20 on the basis of the command CMD or the data, DATA, received from the host 10. The pattern information PT may represent a random operation or a sequential operation. The pattern detector 222 may transmit the pattern information PT to the lower-power mode entry controller 235.” [0042] “The lower-power mode entry controller 235 may control entry of the storage device 20 or the memory controller 200 into a low-power mode,” wherein the “first mode” is the default/standard operating mode of the storage device prior to entering into one of the other “low-power modes”.);
transition from the first mode to a second mode in response to the one or more commands being associated with the first pattern ([0088] “the lower-power mode entry controller 235 may determine whether the low-power mode is to be entered on the basis of at least one among the operation information OP, the pattern information PT, and the speed information SP, and may select one of a plurality of low-power modes when it is determined that the low-power mode is to be entered.”); and
adjust, while operating in the second mode, a rate of at least one clock of the plurality of clocks in accordance with the first pattern ([0116] “the first low-power mode may be a mode of lowering an operating clock frequency of the storage device 20.”).
With further regard to Claim 2, Cheong does not teach the plurality of clocks as described in claim 2. Ware teaches
wherein at least one memory device of the one or more memory devices comprises a plurality of clocks ([0126] “FIG. 12A illustrates an embodiment of a fast-wake memory system 800 having a single controller IC 804 and multiple memory ICs 807... the memory devices (collectively, 807) are disposed on a memory module 805 (generally, a circuit board having an edge connector for removable connection to a backplane or motherboard, and thus permitting memory capacity expansion as additional memory modules are inserted) and individually include an I/O interface and clock distribution arrangement as shown in FIG. 4.” [0073] “Memory-state logic 341 similarly asserts clock-enable signals EnCCK, EnMCK1, EnMCK4 and EnCK to enable clock drivers... to output the memory core clock (CCK), frequency-divided memory I/O clock (MCK1), bit-rate memory I/O clock (MCK4), and controller-forwarded I/O clock (CK), respectively,” wherein “memory-state logic 341” is within “memory device 253”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Cheong with the plurality of clocks as taught by Ware so that “the wake-up latency and thus the worst-case memory access latency is dramatically reduced” (Ware [0039]).
With regard to Claim 4, Cheong in view of Ware teaches all the limitations of Claim 2 as described above. Ware teaches further comprising:
one or more queues coupled with the one or more controllers and the one or more memory devices, wherein the one or more controllers are further configured to cause the memory system to: store, in response to receiving the one or more commands, the one or more commands in a queue of the one or more queues, wherein transitioning from the first mode to the second mode is in accordance with the queue storing the one or more commands ([0032] “FIG. 1, controller core 112 includes a transaction queue 115... Transaction queue 115 is provided to buffer and control servicing of host requests (i.e., requests to store/retrieve memory from the memory system)... Power-mode logic 119 monitors the status or fill-level of transaction queue 115 to determine whether and when to transition memory system 100 between active and sleep modes... power-mode logic 119 transitions the memory system to sleep mode upon determining that the transaction queue has remained empty... for a predetermined number of core-clock cycles” [0067] “power-state logic circuits 271 and 341 are provided within memory controller and memory device, respectively, to manage the transition between active-mode operation and one or more reduced-power states. In one embodiment, the controller-state logic or ‘controller-state logic’ 271 monitors the state of a transaction queue within controller core 252.” [0121] “when the controller 130 detects... a change in a command queue state, the controller 130 may determine an optimal clock frequency which can minimize power consumption while satisfying the required performance of the memory system 110.”).
With regard to Claim 5, Cheong in view of Ware teaches all the limitations of Claim 2 as described above. Cheong further teaches wherein the one or more controllers are further configured to cause the memory system to:
calculate, in response to receiving the one or more commands and while operating in the second mode, a throughput of the one or more commands ([0038] “The host interface 220 may output at least one among a plurality of pieces of control information OP, PT, and SP on the basis of the data, DATA, or the command CMD received from the host 10... speed information SP representing a throughput of the host 10 per unit time... the host interface 220 may measure the throughput of the host 10 per unit time by counting blocks of the data, DATA, received per unit time, and generate the speed information SP. The host interface 220 may transmit at least one among the plurality of pieces of control information OP, PT, and SP to a lower-power mode entry controller (LPMEC) 235.”),
wherein adjusting the rate of the at least one clock is in accordance with the calculated throughput ([0093] “the mode selector 236 may determine whether the low-power mode is to be entered by inserting... the speed information SP into the power table stored in the buffer 300. When it is determined that the low-power mode is to be entered, the mode selector 236 may select a corresponding low-power mode among the plurality of low-power modes.” [0095] “a first low-power mode may be a mode of decreasing an operating clock frequency of the storage device 20.”).
With regard to Claim 8, Cheong in view of Ware teaches all the limitations of Claim 2 as described above. Ware further teaches wherein
the first mode comprises an idle mode of the memory system ([0068] “the system state logic transitions the memory system to a ‘clock-stop’ mode (P3) after idling for `N` core clock cycle,” wherein “mode (P3)” is the “idle mode”.) and
the second mode comprises an analysis mode of the memory system ([0069] “In clock-stop mode P3... considerable power may be saved during relatively brief idle intervals... When a new transaction request is queued, the forwarded I/O clock is re-started within clock-driver 310 to enable a transition directly back to active operating mode, P4,” wherein “mode (P4)” is the “analysis mode”.).
With regard to Claim 9, Cheong teaches a memory system, comprising:
one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to ([0031] “The storage device 20 may include ... a memory controller 200... and a nonvolatile memory 400.”):
receive one or more commands while operating in a first mode ([0037] “the host interface 220 may receive data, DATA, or a command CMD from the host 10.” [0042] “The lower-power mode entry controller 235 may control entry of the storage device 20 or the memory controller 200 into a low-power mode,” wherein the “first mode” is the default/standard operating mode of the storage device prior to entering into one of the other “low-power modes”.);
calculate, in response to receiving the one or more commands and after transitioning from the first mode to a second mode ([0088] “the lower-power mode entry controller 235 may determine whether the low-power mode is to be entered on the basis of at least one among the operation information OP, the pattern information PT, and the speed information SP, and may select one of a plurality of low-power modes when it is determined that the low-power mode is to be entered.”),
a throughput of the one or more commands ([0038] “The host interface 220 may output at least one among a plurality of pieces of control information OP, PT, and SP on the basis of the data, DATA, or the command CMD received from the host 10... speed information SP representing a throughput of the host 10 per unit time... the host interface 220 may measure the throughput of the host 10 per unit time by counting blocks of the data, DATA, received per unit time, and generate the speed information SP. The host interface 220 may transmit at least one among the plurality of pieces of control information OP, PT, and SP to a lower-power mode entry controller (LPMEC) 235.”); and
adjust a rate of each clock of the plurality of clocks in accordance with the calculated throughput of the one or more commands ([0093] “the mode selector 236 may determine whether the low-power mode is to be entered by inserting... the speed information SP into the power table stored in the buffer 300. When it is determined that the low-power mode is to be entered, the mode selector 236 may select a corresponding low-power mode among the plurality of low-power modes.” [0095] “a first low-power mode may be a mode of decreasing an operating clock frequency of the storage device 20.”).
With further regard to Claim 9, Cheong does not teach the plurality of clocks as described in claim 9. Ware teaches
wherein at least one memory device of the one or more memory devices comprises a plurality of clocks ([0126] “FIG. 12A illustrates an embodiment of a fast-wake memory system 800 having a single controller IC 804 and multiple memory ICs 807... the memory devices (collectively, 807) are disposed on a memory module 805 (generally, a circuit board having an edge connector for removable connection to a backplane or motherboard, and thus permitting memory capacity expansion as additional memory modules are inserted) and individually include an I/O interface and clock distribution arrangement as shown in FIG. 4.” [0073] “Memory-state logic 341 similarly asserts clock-enable signals EnCCK, EnMCK1, EnMCK4 and EnCK to enable clock drivers... to output the memory core clock (CCK), frequency-divided memory I/O clock (MCK1), bit-rate memory I/O clock (MCK4), and controller-forwarded I/O clock (CK), respectively,” wherein “memory-state logic 341” is within “memory device 253”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Cheong with the plurality of clocks as taught by Ware so that “the wake-up latency and thus the worst-case memory access latency is dramatically reduced” (Ware [0039]).
With regard to Claim 13, Cheong in view of Ware teaches all the limitations of Claim 9 as described above. Ware further teaches wherein the one or more controllers are further configured to cause the memory system to:
transition, in response to the one or more commands being associated with a first pattern, from the first mode to the second mode ([0088] “the lower-power mode entry controller 235 may determine whether the low-power mode is to be entered on the basis of at least one among the operation information OP, the pattern information PT, and the speed information SP, and may select one of a plurality of low-power modes when it is determined that the low-power mode is to be entered.”),
wherein calculating the throughput of the one or more commands is in accordance with transitioning to the second mode ([0038] “The host interface 220 may output at least one among a plurality of pieces of control information OP, PT, and SP on the basis of the data, DATA, or the command CMD received from the host 10... speed information SP representing a throughput of the host 10 per unit time... the host interface 220 may measure the throughput of the host 10 per unit time by counting blocks of the data, DATA, received per unit time, and generate the speed information SP. The host interface 220 may transmit at least one among the plurality of pieces of control information OP, PT, and SP to a lower-power mode entry controller (LPMEC) 235.”).
With regard to Claims 14-15, these claims are equivalent in scope to Claims 4 and 8 rejected above, merely having a different independent claim type, and as such Claims 14-15 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 4 and 8.
With regard to Claim 16, Cheong teaches a memory system, comprising:
one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to ([0031] “The storage device 20 may include ... a memory controller 200... and a nonvolatile memory 400.”):
receive, while operating in a first mode, one or more commands associated with a first pattern ([0037] “the host interface 220 may receive data, DATA, or a command CMD from the host 10.” [0038] “the host interface 220 may generate the operation information OP or the pattern information PT on the basis of the data.” [0083] “The pattern detector 222 may generate pattern information PT of an operation to be performed by the storage device 20 on the basis of the command CMD or the data, DATA, received from the host 10. The pattern information PT may represent a random operation or a sequential operation. The pattern detector 222 may transmit the pattern information PT to the lower-power mode entry controller 235.” [0042] “The lower-power mode entry controller 235 may control entry of the storage device 20 or the memory controller 200 into a low-power mode,” wherein the “first mode” is the default/standard operating mode of the storage device prior to entering into one of the other “low-power modes”.);
transition from the first mode to a second mode in accordance with the one or more commands being associated with the first pattern ([0088] “the lower-power mode entry controller 235 may determine whether the low-power mode is to be entered on the basis of at least one among the operation information OP, the pattern information PT, and the speed information SP, and may select one of a plurality of low-power modes when it is determined that the low-power mode is to be entered.”);
calculate, in response to receiving the one or more commands and while operating in the second mode, a throughput of the one or more commands ([0038] “The host interface 220 may output at least one among a plurality of pieces of control information OP, PT, and SP on the basis of the data, DATA, or the command CMD received from the host 10... speed information SP representing a throughput of the host 10 per unit time... the host interface 220 may measure the throughput of the host 10 per unit time by counting blocks of the data, DATA, received per unit time, and generate the speed information SP. The host interface 220 may transmit at least one among the plurality of pieces of control information OP, PT, and SP to a lower-power mode entry controller (LPMEC) 235.”); and
adjust a rate of each clock of the plurality of clocks in accordance with the calculated throughput of the one or more commands ([0093] “the mode selector 236 may determine whether the low-power mode is to be entered by inserting... the speed information SP into the power table stored in the buffer 300. When it is determined that the low-power mode is to be entered, the mode selector 236 may select a corresponding low-power mode among the plurality of low-power modes.” [0095] “a first low-power mode may be a mode of decreasing an operating clock frequency of the storage device 20.”).
With further regard to Claim 16, Cheong does not teach the plurality of clocks as described in claim 16. Ware teaches
wherein at least one memory device of the one or more memory devices may comprise a plurality of clocks ([0126] “FIG. 12A illustrates an embodiment of a fast-wake memory system 800 having a single controller IC 804 and multiple memory ICs 807... the memory devices (collectively, 807) are disposed on a memory module 805 (generally, a circuit board having an edge connector for removable connection to a backplane or motherboard, and thus permitting memory capacity expansion as additional memory modules are inserted) and individually include an I/O interface and clock distribution arrangement as shown in FIG. 4.” [0073] “Memory-state logic 341 similarly asserts clock-enable signals EnCCK, EnMCK1, EnMCK4 and EnCK to enable clock drivers... to output the memory core clock (CCK), frequency-divided memory I/O clock (MCK1), bit-rate memory I/O clock (MCK4), and controller-forwarded I/O clock (CK), respectively,” wherein “memory-state logic 341” is within “memory device 253”.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Cheong with the plurality of clocks as taught by Ware so that “the wake-up latency and thus the worst-case memory access latency is dramatically reduced” (Ware [0039]).
With regard to Claims 20-21, these claims are equivalent in scope to Claims 4 and 8 rejected above, merely having a different independent claim type, and as such Claims 20-21 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 4 and 8.
Claims 3, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong in view of Ware as applied to Claims 2, 9 and 16 above, and further in view of Kim et al. (US PGPUB 2022/0334769).
With regard to claim 3, Cheong in view of Ware teaches all the limitations of claim 2 as described above. Cheong in view of Ware does not teach the receiving of read and write command patterns and associated clock adjustment as described in claim 3. Kim teaches
wherein the first pattern comprises a read command pattern, wherein the one or more controllers are further configured to cause the memory system to ([0070] “the processor 134 may control... a read operation of the memory device 150 in response to a read request from the host 102.” [0024] “The host request pattern may include the type and pattern of a command received from a host, the type of the command may include a read type... and the pattern of the command may include a sequential pattern and a random pattern.”):
receive, while operating in the second mode and after adjusting the rate of the at least one clock, one or more second commands associated with a second pattern, wherein the second pattern comprises a write command pattern ([0051] “The controller 130 according to an embodiment may adaptively determine the optimal clock frequency for each operation module, on the basis of changes in the host request pattern,” wherein the patterns of access are associated with the modes as taught above in Cheong. [0024] “The host request pattern may include the type and pattern of a command received from a host, the type of the command may include... a write type, and the pattern of the command may include a sequential pattern and a random pattern.”); and
adjust, in response to the one or more second commands being associated with the second pattern, the rate of at least one of the plurality of clocks in accordance with the second pattern ([0113] “When any of the host request pattern, the command queue state and the current performance is changed, the clock determiner 246 may change the optimal clock frequency set by performing the operations of FIG. 5 again, starting from operation S502.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Cheong in view of Ware with the receiving of read and write command patterns and associated clock adjustment as taught by Kim for purposes of “reducing power consumption while satisfying a required performance” (Kim [0005]).
With regard to Claims 12 and 19, these claims are equivalent in scope to Claims 3 rejected above, merely having a different independent claim type, and as such Claims 12 and 19 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 3.
Claims 6, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong in view of Ware as applied to Claims 5, 9 and 16 above, and further in view of Jang et al. (US PGPUB 2016/0050111).
With regard to claim 6, Cheong in view of Ware teaches all the limitations of claim 5 as described above. Cheong in view of Ware does not teach the selection of a clock frequency based on a calculated throughput as described in claim 6. Jang teaches wherein the one or more controllers are further configured to cause the memory system to:
select, in accordance with the calculated throughput, an index range of frequencies for each clock of the plurality of clocks, wherein adjusting the rate of the at least one clock of the plurality of clocks is in accordance with a respective index range of frequencies of the at least one clock ([0054] “The throughput controller 230 may analyze the calculated throughput output from the throughput monitoring unit 220 to determine the clock frequency of a corresponding driver device or change the operation setup values of the hardware. The throughput controller 230 may include tables that store the clock frequencies or the hardware operation setup values according to the throughput,” wherein the tables, i.e. ‘Table 5’ below [0081] and ‘Table 6’ below [0118], show example demonstrating the “index range of frequencies for each clock”. [0127] “the throughput controller may select one of the configuration settings from the set based on a predetermined criterion and re-configure the electronic device in accordance with the selected configuration setting.” [0081] “the table may include the throughput values to be triggered, and the CPU frequency/bus frequency/IRQ affinity setup value/task affinity setup value.” [0088] “the clock/affinity controller 830 may analyze the parsed throughput message to determine the driver device, and may determine the clock frequency values corresponding to the throughput in the setup value table of the determined driver device.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Cheong in view of Ware with the selection of a clock frequency based on a calculated throughput as taught by Jang since “it is difficult to configure and correct the frequency, and it may bring about the problem of timing due to a difference in the implementation methods of the drivers” (Jang [0006]), wherein the clock frequency selection scheme in Jang is one solution to this issue.
With regard to Claims 10 and 17, these claims are equivalent in scope to Claim 6 rejected above, merely having a different independent claim type, and as such Claims 10 and 17 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claim 6.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cheong in view of Ware as applied to Claim 5 above, and further in view of Kwon et al. (US PGPUB 2022/0398039).
With regard to claim 7, Cheong in view of Ware teaches all the limitations of claim 5 as described above. Cheong in view of Ware does not teach calculating the throughput in accordance with the pattern and command quantity information as described in claim 7. Kwon teaches
wherein the throughput is calculated in accordance with the first pattern and a quantity of the one or more commands ([0070] “The throughput monitor 322 may determine the data throughput due to the data IO operation based on the amount of write data per unit amount of time and the amount of read data per unit amount of time.” [0072] “The workload pattern analyzer 324 may determine whether a data throughput due to the current data IO operation obtained from the throughput monitor 322 is lower than the maximum throughput required under a current workload pattern.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Cheong in view of Ware with calculating the throughput in accordance with the pattern and command quantity information as taught by Kwon in order to “efficiently use the internal resource by further performing the selected internal task while performing the IO task” (Kwon [0123]).
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cheong in view of Ware and Jang as applied to Claims 10 and 17 above, and further in view of Kwon.
With regard to claim 11, Cheong in view of Ware and Jang teaches all the limitations of claim 10 as described above. Cheong in view of Ware and Jang does not teach calculating the throughput in accordance with the pattern and command quantity information as described in claim 11. Kwon teaches
wherein the throughput is calculated in accordance with a first pattern associated with the one or more commands and a quantity of the one or more commands ([0070] “The throughput monitor 322 may determine the data throughput due to the data IO operation based on the amount of write data per unit amount of time and the amount of read data per unit amount of time.” [0072] “The workload pattern analyzer 324 may determine whether a data throughput due to the current data IO operation obtained from the throughput monitor 322 is lower than the maximum throughput required under a current workload pattern.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the system as disclosed by Cheong in view of Ware and Jang with calculating the throughput in accordance with the pattern and command quantity information as taught by Kwon in order to “efficiently use the internal resource by further performing the selected internal task while performing the IO task” (Kwon [0123]).
With regard to Claim 18, this claim is equivalent in scope to Claim 11 rejected above, merely having a different independent claim type, and as such Claim 18 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Thumma (US PGPUB 2014/0344597) discloses systems, methods, and apparatus for dynamically scaling a clock frequency of an I/O interface to a non-volatile storage device based on monitoring an idle time on the I/O interface, a priority of read/write requests queued for dispatch, and a load of the queued read/write requests.
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/NICHOLAS J SIMONETTI/ Primary Examiner, Art Unit 2137 April 10, 2026
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