DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-18 in the reply filed on 8/4/2026 is acknowledged.
Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8-17 are rejected under 35 U.S.C. 102a2 as being anticipated by Shimizu et al (US Pat. 12,249,389; hereinafter referred to as Shimizu).
As per claim 1:
Shimizu teaches a method performed by a storage device (Fig. 1, 30), the method comprising:
performing a read operation to obtain data stored on the storage device (Fig. 12, S10);
performing a decoding operation on the data (Fig. 2, 20);
identifying a refined hard bit read voltage (Figs. 7 and 10, shift value Vst see also Fig. 12, S21; col. 20, line 67-col. 21, line 2) based on constructed data (Fig. 7, error corrected data; corrected data is reconstructed by decoder 21 as described in col. 6, lines 29-35 and col. 12, line 63-col. 13, line 1); and
applying the refined hard bit read voltage (col. 21, lines 5-8 and col. 19, lines 7-9).
As per claims 2, 13:
Shimizu teaches the method of claim 1 and system of claim 12 above, wherein performing the decoding/multiple read operation on the data comprises attempting a hard bit read operation (Fig. 12, S10) using a hard bit read voltage (Fig. 5, AR(0)); and performing a soft bit read operation (Fig. 12, S13) based on failure of the hard bit read operation using the hard bit read voltage (Fig. 12, S11 No).As per claim 3: Shimizu teaches the method of claim 2, wherein the hard bit read voltage is associated with one or more of: a default hard bit read voltage (Fig. 5, AR(0)), or a previously refined hard bit read voltage associated with a previous read operation (Fig. 12, S22).
As per claim 4: Shimizu teaches the method of claim 2, wherein the constructed data comprises data constructed based on the soft bit read operation (col. 12, line 63-col. 13, line 1).
As per claims 5, 14: Shimizu teaches the method of claim 1 and system of claim 12 above, wherein the refined hard bit read voltage is an analog value of voltage (Fig. 10A, Vdif1) associated with determining a bit value of a sensed voltage of the storage device (Fig. 10A, Er and A).
As per claims 6, 15: Shimizu teaches the method of claim 1 and system of claim 12 above, comprising: performing a subsequent read operation (Fig. 12, S22 Yes); and performing a subsequent decoding operation using the refined hard bit read voltage (Fig. 12, loopback beginning with step S10).
As per claim 8: Shimizu teaches the method of claim 6, wherein performing the decoding operation comprises performing a soft bit read operation (Fig. 12, S13) based on failure of a hard bit read operation (Fig. 12, S11 No) using a hard bit read voltage (Fig. 5, AR(0)), and wherein performing the subsequent decoding operation (Fig. 12, S22 Yes loopback) comprises successfully performing a hard bit read operation without a soft bit read operation (Fig. 12, S11 Yes).
As per claim 9: Shimizu teaches the method of claim 1, wherein the storage device comprises a solid state drive (SSD) (col. 3, lines 23-24).
As per claim 10: Shimizu teaches the method of claim 1, wherein the storage device comprises a controller that includes one or more of an application specific integrated circuit (ASIC) or firmware configured to perform operations on the storage device (col. 5, lines 5-11).
As per claims 11, 17: Shimizu teaches the method of claim 1 and system of claim 12 above, comprising: providing the constructed data to an associated host device after the decoding operation (Fig. 1, 2).
As per claim 12:
Shimizu teaches a system comprising:
a controller (Fig. 1, 10), of a non-volatile memory device (Fig. 1, 30), to:
perform multiple read operations (Fig. 12, S10 and S13) to obtain data stored on the storage device (Fig. 12, S14);
perform a decoding operation on the data (Fig. 12, S15 soft bit decoding);
generate constructed data using the multiple read operations and the decoding operation (col. 12, line 63-col. 13, line 1);
identify a refined hard bit read voltage based on constructed data (Fig. 12, S21; col. 20, line 67-col. 21, line 2); and
apply the refined hard bit read voltage (col. 21, lines 5-8 and col. 19, lines 7-9).
As per claim 16:
Shimizu teaches the system of claim 12, wherein the controller is to: generate the constructed data without performing read operations (constructed data is performed by ECC circuit 14 using known ECC techniques which inherently does not require any additional reads).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu in view of Sharon et al (US Pat. Pub. 2015/0339186; hereinafter referred to as Sharon).
As per claim 7:
Shimizu teaches the method of claim 6 above. Not explicitly disclosed is comprising: combine read data and XOR data to generate the constructed data. However, Sharon in an analogous art teaches reconstructing read data with parity using XOR operations (paragraph 59).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filling date to use the parity scheme of Sharon in the memory of Shimizu. This modification would have been obvious for one of ordinary skill in the art at the time of filing because parity is suggested by Shimizu (col. 4, lines 32-35).
Allowable Subject Matter
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Shimizu teaches generating constructed data as detailed above. However, none of the prior art of record teach or fairly suggest that generating the constructed data comprises: identifying locations of conflicting bit values between a first read operation and a second read operation; and generating the constructed data to include bit values of the first read operation at locations without conflicting bit values and to include bit values of the second read operation at locations having conflicting bit values as recited by claim 18; particularly in combination with each and every limitation of parent claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art are directed to techniques for updating read voltages in non-volatile memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111
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