DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-11 and 16-20 are considered indefinite because it is unclear if the recited “avalanche photodiode,” “avalanche diode,” and “diode” refer to the same element. If so, please change to one descriptor consistently throughout the claims.
Claim 16 is also considered indefinite because it recites “a plurality of avalanche diodes…which are disposed at different respective locations…and are configured.” It is not clear what is meant by “are configured.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 10, 11, and 16-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ota (JP 2018157387 A).
Regarding Claim 1: Ota discloses a sensing device, comprising:
an array of sensing elements (10), each sensing element comprising:
a photosensitive material, which is configured to generate photoelectrons in response to incident optical radiation (Fig. 4, 224; [0034]: “The n-type semiconductor region 224 is a photoelectric conversion region that generates carriers upon the incidence of photons.”); and
a plurality of avalanche diodes, which are disposed at different, respective locations within the sensing element in electrical communication with the photosensitive material and are configured, when reverse-biased, to generate electrical avalanches in response to the generated photoelectrons (Figs. 3, 4; [0028]: “Each of the n-type semiconductor regions 224 separated by the separation unit 220 is equipped with multiple avalanche photodiodes (APDs) that are contained within a single pixel 12.”); and
a bias control circuit, which is configured to selectively set respective reverse-bias voltage levels of the avalanche diodes within each sensing element to different, respective values ([0056]: “The gain control switch (N-type MOS transistor MN) is a setting means that individually sets multiple avalanche photodiodes to an active or inactive state.”; [0046]: “Thus, the N-type MOS transistor MN is a switch that changes the voltage applied to the avalanche photodiode APD to a voltage higher than or below the breakdown voltage of the avalanche photodiode APD.”).
Regarding Claim 2: Ota discloses the device according to claim 1, wherein the plurality of avalanche diodes comprises a respective plurality of disjoint p-n junctions (Fig. 4).
Regarding Claim 3: Ota discloses the device according to claim 1, wherein the plurality of avalanche diodes comprises a continuous p-n junction with multiple disjoint electrodes patterned to define the p-n junction (Fig. 4).
Regarding Claim 4: Ota discloses the device according to claim 1, wherein the bias control circuit is configured to selectively set the respective reverse-bias voltage levels so that at least one of the avalanche photodiodes in a given sensing element is set to a reverse-bias voltage level greater than a breakdown voltage of the avalanche diodes and another of the avalanche diodes in the given sensing element is set to a reverse-bias voltage lower than the breakdown voltage of the avalanche diodes (Fig. 8; [0046]: “Thus, the N-type MOS transistor MN is a switch that changes the voltage applied to the avalanche photodiode APD to a voltage higher than or below the breakdown voltage of the avalanche photodiode APD.”; [0056]-[0057]).
Regarding Claim 5: Ota discloses the device according to claim 4, wherein the bias control circuit is configured to set the reverse-bias voltage lower than the breakdown voltage of the avalanche diodes by electrically grounding the avalanche diodes (Fig. 3; [0045]).
Regarding Claim 6: Ota discloses the device according to claim 1, wherein each sensing element comprises a switching circuit, which is configured to apply the same reverse-bias voltage level to a group of the avalanche diodes in the sensing element (Fig. 8; Fig. 9; [0070]: “…the switch SW is also a setting means for individually setting multiple avalanche photodiodes to an active or inactive state.”).
Regarding Claim 7: Ota discloses the device according to claim 1, wherein the avalanche diodes in each sensing cell comprise a central photodiode surrounded by a plurality of peripheral photodiodes (Fig. 8).
Regarding Claim 8: Ota discloses the device according to claim 1, wherein each sensing element comprises a switching circuit comprising multiple inverters (Fig. 3, INV1, INV2, INV3) coupled to respective sets of one or more of the avalanche diodes and an OR gate coupled to merge respective outputs of the multiple inverters (112).
Regarding Claim 10: Ota discloses the device according to claim 1, wherein the plurality of diodes give rise to a total effective active area of each sensing element, and wherein by selectively setting respective reverse-bias voltage levels, the control circuit is configured to change the total effective active area (Figs. 10b and 10c).
Regarding Claim 11: Ota discloses the device according to claim 1, wherein each diode of the plurality of diodes is coupled to a respective switching circuit and a readout circuitry comprising an inverter (Fig. 3).
Regarding Claim 16: Ota discloses a sensing method, comprising:
in an array of sensing elements (10), in each sensing element of the array:
generating photoelectrons in response to incident optical radiation using a photosensitive material (Fig. 4, 224; [0034]: “The n-type semiconductor region 224 is a photoelectric conversion region that generates carriers upon the incidence of photons.”); and
generating electrical avalanches in response to the generated photoelectrons using a plurality of avalanche diodes, when reverse-biased, which are disposed at different, respective locations within the sensing element in electrical communication with the photosensitive material and are configured ([0042]: “These electrons are accelerated by the electric field in the n-type semiconductor region 226, causing avalanche amplification, and the avalanche photodiode (APD) operates in Geiger mode.); and
selectively setting respective reverse-bias voltage levels of the avalanche diodes within each sensing element to different, respective values ([0056]: “The gain control switch (N-type MOS transistor MN) is a setting means that individually sets multiple avalanche photodiodes to an active or inactive state.”; [0046]: “Thus, the N-type MOS transistor MN is a switch that changes the voltage applied to the avalanche photodiode APD to a voltage higher than or below the breakdown voltage of the avalanche photodiode APD.”).
Regarding Claim 17: Ota discloses the sensing method according to claim 16, wherein the plurality of avalanche diodes comprises a respective plurality of disjoint p-n junctions (Fig. 4).
Regarding Claim 18: Ota discloses the sensing method according to claim 16, wherein selectively setting the respective reverse-bias voltage levels comprises setting at least one of the avalanche photodiodes in a given sensing element to a reverse-bias voltage level greater than a breakdown voltage of the avalanche diodes and setting another of the avalanche diodes in the given sensing element to a reverse-bias voltage lower than the breakdown voltage of the avalanche diodes (Fig. 8; [0046]: “Thus, the N-type MOS transistor MN is a switch that changes the voltage applied to the avalanche photodiode APD to a voltage higher than or below the breakdown voltage of the avalanche photodiode APD.”; [0056]-[0057]).
Regarding Claim 19: Ota discloses the sensing method according to claim 16, wherein selectively setting the respective reverse-bias voltage levels comprises applying the same reverse-bias voltage level to a group of the avalanche diodes in the sensing element (Fig. 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ota in view of Sakimura (US 12468019 B2).
Regarding Claim 9: Ota discloses the device according to claim 1, wherein each sensing element comprises a switching circuit comprising multiple inverters coupled to respective sets of one or more of the avalanche diodes (Figs. 3 and 9), but Ota fails to teach respective one-shot circuits coupled to the inverters, and an OR gate coupled to merge respective outputs of the one-shot circuits.
Sakimura teaches one-shot circuits (Fig. 18, 26) coupled to the inverters (Fig. 16, 24), and an OR gate coupled to merge respective outputs of the one-shot circuits (Fig. 18, 32).
It would have been obvious to someone of ordinary skill in the art to have modified Ota to incorporate the teachings of Sakimura and provide one-shot circuits between the inverter and OR gate. One would be motivated to make such a modification on the basis of reducing the output pulse width, thereby reducing dead time following the firing of each SPAD.
Regarding Claim 20: Ota discloses the sensing method according to claim 16, wherein each sensing element comprises a switching circuit comprising multiple inverters coupled to respective sets of one or more of the avalanche diodes (Figs. 3 and 9, but Ota fails to teach respective one-shot circuits coupled to the inverters, and an OR gate coupled to merge respective outputs of the multiple one-shot circuits.
Sakimura teaches one-shot circuits (Fig. 18, 26) coupled to the inverters (Fig. 16, 24), and an OR gate coupled to merge respective outputs of the one-shot circuits (Fig. 18, 32).
It would have been obvious to someone of ordinary skill in the art to have modified Ota to incorporate the teachings of Sakimura and provide one-shot circuits between the inverter and OR gate. One would be motivated to make such a modification on the basis of reducing the output pulse width, thereby reducing dead time following the firing of each SPAD.
Claim(s) 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ota in view of Verghese (US 20210088681 A1).
Regarding Claim 12:Ota discloses the device according to claim 1, but fails to teach wherein the photosensitive material is configured to generate the photoelectrons in response to near infrared (NIR) optical radiation.
Verghese teaches a photosensitive material is configured to generate the photoelectrons in response to near infrared (NIR) optical radiation ([0030]: “…the SPADs 122 could be configured to detect infrared light (e.g., 905 nm or 1550 nm).”).
It would be obvious to someone of ordinary skill in the art to have modified Ota to incorporate the teachings of Verghese and configure the photosensitive material to generate photoelectrons in response to near infrared optical radiation. One would be motivated to make such a modification on the basis that NIR wavelengths are commonly used in optical sensing applications.
Regarding Claim 13: Ota discloses the device according to claim 12, wherein the photosensitive material comprises silicon (Ota: [0027]).
Regarding Claim 14: Ota discloses the device according to claim 1, wherein the photosensitive material is configured to generate the photoelectrons in response to short wave infrared (SWIR) radiation.
Verghese teaches a photosensitive material is configured to generate the photoelectrons in response to short wave infrared (SWIR) optical radiation ([0030]: “…the SPADs 122 could be configured to detect infrared light (e.g., 905 nm or 1550 nm).”).
It would be obvious to someone of ordinary skill in the art to have modified Ota to incorporate the teachings of Verghese and configure the photosensitive material to generate photoelectrons in response to near infrared optical radiation. One would be motivated to make such a modification on the basis of improving performance under low-light conditions.
Regarding Claim 15: Ota discloses the device according to claim 13, wherein the photosensitive material comprises germanium (Verghese: [0028]).
Conclusion
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/MIYA DOWNING/Examiner, Art Unit 2884
/DAVID J MAKIYA/Supervisory Patent Examiner, Art Unit 2884
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