DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4 and 14 recite on the third line, “transferring the port number to another memory module,” and it is unclear as to what the Applicant intends for this claim element to recite, since, given the context of the surrounding claim language, it is unlikely that the intended meaning is a step of transferring/transmitting the numeric value of the ”port number” to another “memory module”. Instead, based on the context of the claim language, and for purposes of examination, the Office has interpreted this limitation as instead meaning “transferring the [optical link frame] to another memory module,” since the “routing ID” of the “optical link frame” was changed to “a port number of the optical module from which the optical link frame has been received,” in the immediately previous step. See also Claims 3 and 13 which recite a similar step, i.e. “transmit the optical link frame to another memory module...”.
Appropriate correction is required to Claims 4 and 14 to resolve the indefiniteness discussed above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims recite methods and systems for accessing memory based on received address information.
The limitations in Independent Claims 1 and 11 of interpreting received information and making a determination based on the received information, as drafted, are processes that, under their broadest reasonable interpretation, covers steps that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. That is, the limitations of “interpreting the optical link frame,” and “determining whether a physical address included in the optical link frame corresponds to a physical address of a shared memory owned by a memory module included in the memory node” in Claims 1 and 11, as drafted, are processes that, under their broadest reasonable interpretation, recite the abstract idea of mental processes. These limitations encompass a human mind carrying out these functions through observation, evaluation judgment and/or opinion, or even with the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas.
This judicial exception is not integrated into a practical application. The claims recite the following additional elements “receiving... an optical link frame including a request of at least one of the CPU node and the accelerator node from an optical module,” in Claims 1 and 11, these limitations do nothing more than add insignificant extra solution activity to the judicial exception, such as data gathering and outputting the results of the abstract idea, see MPEP 2106.05(g).
Further, the “accessing the shared memory connected to an optical link matcher when the physical address included in the optical link frame corresponds to the physical address of the shared memory owned by the memory module” elements of Claims 1 and 11, as well as the “receiving, by the memory node,” element of Claim 1 and “a memory including an instruction; and a processor configured to, by executing the instruction...” elements of Claim 11, are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, see MPEP 2106.05(f). Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea, thus failing to integrate the abstract idea into a practical application.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements which recite “accessing the shared memory...” in Claims 1 and 11, the “receiving, by the memory node,” element of Claim 1, and the “memory...” and “processor...” elements of Claim 11, amount to no more than mere instructions to apply the exception using well-known, routine and conventional generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. Additionally, the “receiving...” step recites a form of “receiving or transmitting data over a network” and the “accessing...” step recites a form of “Storing and retrieving information in memory”, which the courts have found to be well-understood, routine, and conventional activities, see MPEP 2106.05(d)(II). Thus, Claims 1 and 11 are not patent eligible under 35 U.S.C.101.
With regard to the individual dependent claims:
Claim 2 recites, “wherein the determining of whether the physical address included in the optical link frame corresponds to the physical address of the shared memory owned by the memory module includes determining whether the physical address included in the optical link frame corresponds to the physical address of the shared memory owned by the memory module using a routing ID of the optical link frame.”
Claims 4 and 14 recite, “changing a routing ID of the optical link frame to a port number of the optical module from which the optical link frame has been received... when the physical address included in the optical link frame does not correspond to the physical address of the shared memory owned by the memory module.”
Claim 12 recites, “....determine whether the physical address included in the optical link frame corresponds to the physical address of the shared memory owned by the memory module using a routing ID of the optical link frame.”
These limitations of Claims 2, 4, 12 and 14, as drafted, are processes that, under their broadest reasonable interpretation, recite the abstract idea of a mental process. These limitations encompass a human mind carrying out this function through observation, evaluation judgment and/or opinion, or even with the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
Claims 3 and 13 recite, “transmitting the optical link frame to another memory module having the physical address included in the optical link frame, when the physical address included in the optical link frame does not correspond to the physical address of the shared memory owned by the memory module.”
Claims 4 and 14 further recite, “transferring the port number to another memory module”.
Claims 5 and 15 recite, “wherein the request includes at least one of memory read, memory write, and priority,” which modifies the recitation in Claims 1 and 11 of “receiving... an optical link frame including a request”.
Claims 7 and 17 recite, “wherein the optical link frame includes a write request optical link frame used when the CPU node or the accelerator node requests data write to the shared memory located in the memory node, and the write request optical link frame includes a 4-bit OP_Code field, a 4-bit priority field, a 4-bit routing ID field, a 12-bit Req_Size field, a 40-bit Seq_Num field, a 40-bit Address field, a Payload field of at least 1 byte, and a 16-bit End-to-end Cyclic Redundancy Check (ECRC) field,” which modifies the recitation in Claims 1 and 11 of “receiving... an optical link frame including a request”.
Claims 8 and 18 recite, “wherein the optical link frame includes a read request optical link frame used when the CPU node or the accelerator node requests data read from the shared memory located in the memory node, and the read request optical link frame includes a 4-bit OP_Code field, a 4-bit priority field, a 4-bit routing ID field, a 12-bit Req_Size field, a 40-bit Seq_Num field, a 40-bit Address field, and a 16-bit ECRC field,” which modifies the recitation in Claims 1 and 11 of “receiving... an optical link frame including a request”.
Claims 9 and 19 recite, “wherein the optical link frame includes a write response optical link frame for an optical link frame requested by the CPU node or the accelerator node to use shared memory located in the memory node, the write response optical link frame includes a 4-bit OP_Code field, a 4-bit priority field, a 4-bit routing ID field, a 12-bit Payload_Size field, a 40-bit Seq_Num field, an 8-bit Reserved field, and a 16-bit ECRC field,” which modifies the recitation in Claims 1 and 11 of “receiving... an optical link frame including a request”.
Claims 10 and 20 recite, “wherein the optical link frame includes a read response optical link frame for an optical link frame requested by the CPU node or the accelerator node to use shared memory located in the memory node, the read response optical link frame includes a 4-bit OP_Code field, a 4-bit priority field, a 4-bit routing ID field, a 12-bit Req_Size field, a 40-bit Seq_Num field, a Payload field of at least 1 byte, a 8-bit Reserved field, and a 16-bit ECRC field,” which modifies the recitation in Claims 1 and 11 of “receiving... an optical link frame including a request”.
These limitations of Claims 3-5, 7-10, 13-15 and 17-20 do nothing more than add insignificant extra solution activity to the judicial exception, such as data gathering and outputting the results of the abstract idea, see MPEP 2106.05(g). Additionally, the above limitations recite steps of “receiving or transmitting data over a network” (Claims 3-4 and 13-14), which the courts have found to be a well-understood, routine, and conventional activity, see MPEP 2106.05(d)(II).
Claims 6 and 16 recite, “wherein the computing system further includes an optical switch, and a plurality of CPUs of the CPU node and a plurality of accelerators of the accelerator node are connected to the shared memory of the memory node through the optical switch and the optical link matcher.”
These limitations of Claims 6 and 16 recite further elements at a high-level of generality such that they amount to no more than mere instructions to apply the exception using generic computer components, see MPEP 2106.05(f). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea and they cannot provide an inventive concept.
As such, for the reasons discussed above, dependent Claims 2-10 and 12-20 are not patent eligible under 35 U.S.C.101.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 11-13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otani et al. (US PGPUB 2012/0047293).
With regard to Claim 1, Otani teaches a method for sharing memory in a computing system including a central processor (CPU) node, an accelerator node, and a memory node, the method comprising:
receiving, by the memory node, an optical link frame including a request of at least one of the CPU node and the accelerator node from an optical module ([0009] “a storage system comprises one or more storage devices; a storage controller having a storage controller processor and a storage controller memory and being coupled with the one or more storage devices; an interface controller receiving an I/O (input/output) command directly from a host computer,” wherein the “storage system” and “host computer” are the “memory node” and “CPU node” respectively. [0011] “the received I/O command includes one or more frames.” "[0045] “The host 200 includes a CPU, a RAM, and a network controller (NC) to connect to the network controller on the storage subsystem 100,” wherein the “network controller (NC)” of the “host 200” is the “optical module”.);
interpreting the optical link frame ([0051] “When the frame forwarder 140 receives the packet/frame, it analyzes the destination address of the packet/frame, refers to the forwarding table 142-03, and then sends the packet/frame to the proper component such as a network controller, another frame forwarder 140, or the storage controller 110 via the internal bus 150.”);
determining whether a physical address included in the optical link frame corresponds to a physical address of a shared memory owned by a memory module included in the memory node ([0007] “If the frame forwarder receives a packet/frame with a destination address for the storage controller within the storage subsystem, the frame forwarder sends the packet/frame to the storage controller,” wherein the “destination address” is the “physical address.” [0008] “Each logical volume is composed by using storage devices which are located on the device unit,” wherein a “logical volume” and associated “storage device” are the “shared memory” and “memory module” respectively, and further wherein the “logical volume” is a shared memory” since it is accessible by a plurality of hosts, i.e. see Otani [0047].); and
accessing the shared memory connected to an optical link matcher when the physical address included in the optical link frame corresponds to the physical address of the shared memory owned by the memory module ([0011] “The interface controller includes... a frame forwarder,” wherein the “interface controller” is the “optical link matcher”. [0052] “FIG. 7 shows an example of the mapping table 112-05 of the storage controller 110... All packets and frames with the destination address ‘Addr110’ will be forwarded to the storage controller 110, and then the storage controller 110 can de-capsulate the packets/frames and proceed with SCSI layer I/O processing,” wherein Fig. 1 of Otani shows the “Interface Controller 130a” coupled to the “Storage Devices” within “Device Unit 120”.).
With regard to Claim 2, Otani teaches the method of claim 1, wherein the determining of whether the physical address included in the optical link frame corresponds to the physical address of the shared memory owned by the memory module includes determining whether the physical address included in the optical link frame corresponds to the physical address of the shared memory owned by the memory module using a routing ID of the optical link frame ([0047] “Each packet/frame has a destination address such as ... routing ID (bus, device function number) for PCI express.” [0049] “FIG. 5b shows an example of the packet/frame format for storage I/O using FCoE over PCI express... The destination address is 00:03:11 (bus/dev/fn ID of the storage controller 110), and the PCI express frame (TLP) is transferred to the storage controller 110 according to the forwarding table 142-03a.”).
With regard to Claim 3, Otani teaches further comprising:
transmitting the optical link frame to another memory module having the physical address included in the optical link frame, when the physical address included in the optical link frame does not correspond to the physical address of the shared memory owned by the memory module ([0063] “When the frame forwarder 140 on a network controller receives a packet/frame, it analyzes the destination address of the packet/frame, refers to the forwarding table 142-03, and then sends the packet/frame to the proper component such as another frame forwarder 140 on another network controller or the storage controller 110 via the internal bus 150,” wherein “another memory module” could be “another frame forwarder 140,” since the “frame forwarders 140” shown in Fig. 1 comprise RAM memory.).
With regard to Claim 5, Otani teaches the method of claim 1, wherein the request includes at least one of memory read, memory write, and priority ([0047] “A host 200 issues a read/write SCSI I/O command to the logical volumes. At first, a network controller on the storage subsystem 100 receives the SCSI I/O command which is encapsulated and divided into one or more packets/frames by using a lower layer protocol such as iSCSI, FCoE (Ethernet), Infiniband, and PCI express. Each packet/frame is transferred to a frame forwarder 140,” wherein the “read/write SCSI I/O command” are the “memory read” and “memory write”.).
With regard to Claims 11-13 and 15, these claims are equivalent in scope to Claims 1-3 and 5 rejected above, merely having a different independent claim type, and as such Claims 11-13 and 15 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 1-3 and 5.
With further regard to Claim 11, the claim recites additional elements not specifically addressed in the rejection of Claim 1. The Otani reference also anticipates these additional elements of Claim 11, for example, wherein the apparatus comprises:
a memory including an instruction ([0065] “the system configurations illustrated in FIGS. 1 and 10 are purely exemplary... The computers and storage systems implementing the invention can also have known I/O devices (e.g., CD and DVD drives, floppy disk drives, hard drives, etc.) which can store and read the modules, programs and data structures used to implement the above-described invention,” wherein the “modules, [and] programs” comprise at least one instruction.); and
a processor configured to, by executing the instruction, [perform operations] ([0037] “a variety of programming languages may be used to implement the teachings of the invention as described herein. The instructions of the programming language(s) may be executed by one or more processing devices, e.g., central processing units (CPUs), processors, or controllers.” [0067] “the operations described above can be performed by hardware, software, or some combination of software and hardware. Various aspects of embodiments of the invention may be implemented using circuits and logic devices (hardware), while other aspects may be implemented using instructions stored on a machine-readable medium (software), which if executed by a processor, would cause the processor to perform a method to carry out embodiments of the invention.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Otani as applied to Claims 1 and 11 above, and further in view of DeSanti (US PGPUB 2014/0307578).
With regard to claim 4, Otani teaches all the limitations of claim 1 as described above. Otani does not teach the changing of a routing ID as described in claim 4. DeSanti teaches
changing a routing ID of the optical link frame to a port number of the optical module from which the optical link frame has been received and transferring the port number to another memory module, when the physical address included in the optical link frame does not correspond to the physical address of the shared memory owned by the memory module ([0027] “The FC frame includes an FC destination identifier ‘D_ID’ that indicates the intended recipient of the FC frame... Typically, the FCF updates source and destination media access control (MAC) addresses of the Ethernet header of the FCoE packet at each hop until the device corresponding to the D_ID is reached. In particular, the source MAC address is changed to the MAC address of the FCF forwarding the packet, and the destination MAC address is changed to the MAC address of either the destination (e.g., D_ID) indicated by the FC destination identifier, or the next FCF on the hop path towards the D_ID. At each hop, the FCF determines the destination MAC address for the next hop based on the D_ID and a routing protocol called Fabric Shortest Path First (FSPF),” wherein the “source MAC address” is “a port number of the optical module from which the optical link frame has been received.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Otani with the changing of a routing ID as taught by DeSanti since this use of Fibre Channel over Ethernet (FCoE) functionality results in a system in which “costs are significantly reduced... and the resulting decrease in network complexity provides a corresponding increase in network reliability” (DeSanti [0022]).
With regard to Claim 14, this claim is equivalent in scope to Claim 4 rejected above, merely having a different independent claim type, and as such Claim 14 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 4.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Otani as applied to Claims 1 and 11 above, and further in view of Guim Bernat et al. (US PGPUB 2019/004910; hereinafter “Guim”).
With regard to claim 6, Otani teaches all the limitations of claim 1 as described above. Otani does not teach the optical switch and connected nodes as described in claim 6. Guim teaches
wherein the computing system further includes an optical switch ([0027] “The various devices in a data center may be connected to each other via a switching fabric 170.” [0029] “each server 146 may have a direct connection to a top-of-rack (ToR) switch 120 (e.g., a “star” configuration), and each ToR switch 120 may couple to a core switch 130.” [0031] “Interconnect technologies include... FibreChannel... FibreChannel over Ethernet (FCoE),” wherein the “core switch” is a type of “optical switch” since it supports the FibreChannel optical interconnect technologies.), and
a plurality of CPUs of the CPU node and a plurality of accelerators of the accelerator node are connected to the shared memory of the memory node through the optical switch and the optical link matcher (See Fig. 1 showing a data center, i.e. “computing system”, comprising, [0025] “workload clusters 118, which may be clusters of individual servers, blade servers, rackmount servers, or any other suitable server topology. In this illustrative example, two workload clusters, 118-1 and 118-2 are shown, each providing rackmount servers 146 in a chassis 148,” wherein the servers/clusters are connected via “Core Switch 130”. [0036] “data center 200 includes a number of logic elements forming a plurality of nodes. It should be understood that each node may be provided by a physical server, a group of servers, or other hardware.” [0037] “Node 0 208 is a processing node including a processor socket 0 and processor socket 1. The processors may be, for example, Intel® Xeon™ processors with a plurality of cores, such as 4 or 8 cores,” wherein “Node 0” is the “CPU node,” see also “Compute Chassis 424-3” in Fig. 4. [0058] “accelerator chassis 430 may host a number of accelerators, such as Intel® Quick Assist™ technology (QAT), FPGAs, ASICs, or other accelerators of the same or different types,” wherein the “accelerator chassis 430” is the “accelerator node”. [0043] “a storage server node 2 210... may provide a networked bunch of disks (NBOD), PFM, redundant array of independent disks (RAID), redundant array of independent nodes (RAIN), network attached storage (NAS),” wherein “storage server node 2” is equivalent to the “memory node” as taught above in Otani. [0030] “each server 146 may include a fabric interface, such as... a network interface card (NIC),” wherein the “NIC”, i.e. “optical link matcher”, is equivalent to the “interface controller” as taught above in Otani.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Otani with the optical switch and connected nodes as taught by Guim since “This kind of distributed architecture... may be advantageous because there is no need to over-provision resources for each node” (Guim [0041]).
With regard to Claim 16, this claim is equivalent in scope to Claim 6 rejected above, merely having a different independent claim type, and as such Claim 16 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Thomas (US PGPUB 2022/0206709) discloses a system comprising circuitry which receives a data communication packet including at least payload data and a target address, and further circuitry which controls writing of the payload data by one or more storage devices addressable by the target address, responsive to the storage classification received with the packet and to respective persistence properties associated with the candidate storage devices.
Koukis et al. (“GMBlock: Optimizing data movement in a block-level storage sharing system over Myrinet,” 2010) discusses a block-level storage shar ing system which uses an optimized I/O path to transfer data directly between the storage medium and the network, including discussion regarding the transmission of data in frames.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J SIMONETTI whose telephone number is (571)270-7702. The examiner can normally be reached Monday-Thursday 10AM-6PM EST.
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/NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 March 19, 2026
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