DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/05/25, 04/01/25 and 09/25/25 has been considered by the examiner.
Drawings
The drawings received on 01/13/25 are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Clendenen et al. (US 9,735,725 B2, hereinafter “Clendenen”) in view of Grombach et al. (US 8,233,253 B2, hereinafter “Grombach”).
Regarding claim 1, Clendenen discloses (see Fig. 2) an inverter (comprising 108, 222),
comprising: a positive input terminal (top terminal of 222 coupled to 124) and a negative input terminal (bottom terminal of 222 coupled to 124) to be coupled to a direct current (DC) voltage source (124) to receive a DC voltage (voltage across 124); an inverter circuit (108) having an input (input to 108 coupled to 222) and an output (output of 108 coupled to 102), wherein the inverter is configured to receive the DC voltage at the input (received via 222) and convert the DC voltage to an alternating current (AC) voltage at the output (AC voltage output to Motor 102); and a transient protection circuit (222) coupled between the positive and negative input terminals and the input of the inverter circuit (222 is coupled between top and bottom terminals of 222 and input to 108) to protect the input of the inverter circuit in response to a surge of the DC voltage (see col. 4, line 15 to col. 5, line 10 "If voltage within transient voltage protection system 200 exceeds a breakdown voltage of Zener diode 242, current flowing through Zener diode 242, first resistor 244, second resistor 246, and third resistor 248 is provided to gate 240 of SCR 234. SCR 234 conducts and functions as a short circuit."), wherein the transient protection circuit comprises: a field-effect transistor (FET) (234, see col. 5, lines 15 to 60 "semiconductor device 234 may be a metal-oxide-semiconductor field-effect transistor (MOSFET)") coupled across the input of the inverter circuit (234 is coupled across the input of 108), a first Zener diode (242) coupled between a positive input of the inverter circuit (top-side input of 108) and the FET (242 is coupled between the top-side input of 108 and the gate of 234). Clendenen does not disclose wherein the transient protection circuit comprises: a second Zener diode coupled between a negative input of the inverter circuit and the FET.
However, Grombach teaches (see Fig. 1) a second Zener diode (24) coupled between a
negative input of the inverter circuit (34 of 30) and the FET (12) (24 is coupled between 34 and the gate of 12).
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the claimed invention to modify the inverter of Clendenen wherein the transient protection circuit comprises: a second Zener diode coupled between a negative input of the inverter circuit and the FET, as taught by Grombach, because it can help clamp the gate voltage of the FET to protect the FET from overvoltage damage.
Regarding claim 2, Clendenen discloses (see Fig. 2) wherein when the DC voltage
exceeds a predetermined threshold (breakdown voltage of Zener diode 242), the FET is turned on to form a substantial short circuit across the input of the inverter circuit (see [0023] "If voltage within transient voltage protection system 200 exceeds a breakdown voltage of Zener diode 242, current flowing through Zener diode 242, first resistor 244, second resistor 246, and third resistor 248 is provided to gate 240 of SCR 234. SCR 234 conducts and functions as a short circuit.").
Regarding claim 3, Clendenen discloses (see Fig. 2) wherein the first Zener diode (242)
is configured to clamp a voltage (breakdown voltage of 242) across the positive input of the inverter circuit (top-side input of 108) and a gate terminal of the FET (240).
Clendenen does not disclose wherein the clamped voltage is within approximately 43 volts.
However, Clendenen teaches that a voltage clamping device is configured to clamp the
voltage to a necessary level to protect the inverter from being damaged, along with an
exemplary voltage range (see col.4, line 60 to col. 5, line 10 "If voltage within transient voltage protection system 200 exceeds a breakdown voltage of Zener diode 242, current flowing through Zener diode 242, first resistor 244, second resistor 246, and third resistor 248 is provided to gate 240 of SCR 234. SCR 234 conducts and functions as a short circuit. Third voltage clamping device 228 is configured to clamp the voltage to a necessary level to protect inverter 108 from being damaged. In the exemplary embodiment, third voltage clamping device 228 clamps the voltage at about 650 VDC or about 300 amps.").
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the claimed invention to modify the clamped voltage to be within
approximately 43 volts, i.e. to be within the operating voltage of 108 and the rated voltages of the components of 222, because it can help clamp the voltage to a necessary level to protect the inverter from being damaged, and further since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 4, Clendenen does not disclose wherein the second Zener diode is
configured to clamp a voltage across the gate terminal of the FET and the negative input of the inverter circuit within 18 volts to prevent overvoltage from occurring across the FET.
However, Grombach teaches (see Fig. 1) wherein the second Zener diode (24) is
configured to clamp a voltage (breakdown voltage of 24) across the gate terminal of the FET (18 of 12) and the negative input of the inverter circuit (34 of 30) to prevent overvoltage from occurring across the FET (24 clamps the voltage across 18 to assure 12 is turned-on which prevents overvoltage occurring across 12).
Therefore, it would have been obvious to one having ordinary skill in the art before the
effective filing date of the claimed invention to modify the protection circuit of Clendenen to include a second Zener diode wherein the second Zener diode is configured to clamp a voltage across the gate terminal of the FET and the negative input of the inverter circuit to prevent overvoltage from occurring across the FET, as taught by Grombach, because it can help clamp the gate voltage of the FET to protect the FET from overvoltage damage. Clendenen modified in view of Grombach does not disclose wherein the clamped gate voltage is within 18 volts.
Regarding claim 5, Clendenen discloses (see Fig. 2) wherein a cathode of the first
Zener diode (cathode of 242) is coupled to a positive input of the inverter circuit (top-side input of 108) and an anode of the first Zener diode (anode of 242) is coupled to a gate terminal of the FET (anode of 242 is coupled to the gate of 234).
Regarding claim 6, Clendenen does not disclose wherein a cathode of the second
Zener diode is coupled to the gate terminal of the FET and an anode of the second Zener diode is coupled to a negative input of the inverter circuit.
However, Grombach teaches (see Fig. 1) wherein a cathode of the second Zener diode
(cathode of 24) is coupled to the gate terminal of the FET (coupled to the gate of 12) and an anode of the second Zener diode (anode of 24) is coupled to a negative input of the inverter circuit (34, anode of 24 is coupled to 34).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the inverter of Clendenen wherein a cathode of the second Zener diode is coupled to the gate terminal of the FET and an anode of the second Zener diode is coupled to a negative input of the inverter circuit, as taught by Grombach, because it can help clamp the gate voltage of the FET to protect the FET from overvoltage damage.
Regarding claim 7, Clendenen discloses (see Fig. 2) wherein the transient protection
circuit further comprises: a first resister (240) coupled between the anode of the first Zener diode and the negative input of the inverter circuit (240 is coupled between the anode of 242 and bottom-side input of 108); and a second resister (244) coupled between the anode of the first Zener diode and the gate terminal of the FET (244 is coupled between the anode of 242 and gate of 234).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No.12,597,853. Although the claims at issue are not identical, they are not patentably distinct from each other because the patented claims anticipates the examined claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zeng et al. (US 2024/0171064 A1) disclose an input transient protection and reverse protection for inverters.
Zeng et al. (US 12,199,501 B2) disclose a pulse by pulse current limit with slope compensator for inverters.
Examiner has cited particular columns, line numbers and/or paragraphs in the
references applied to the claims above for the convenience of the applicant. Although
the specified citations are representative of the teachings of the art and are applied to
specific limitations within the individual claim(s), other passages and figures may apply
as well.
Additionally, in the event that other prior art is provided and made of record by the
Examiner, as being relevant or pertinent to applicant's disclosure but not relied upon. The references are provided for the convenience of the applicant.
The Examiner request that the references be considered in any subsequent amendments, as they are also representative of the art and may apply to the specific limitations of any newly amended claim(s).
It is respectfully requested from the applicant in preparing amendments or responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art and/or disclosed by the Examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7 AM - 10 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
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