Prosecution Insights
Last updated: October 02, 2026
Application No. 19/018,268

MULTILAYER CERAMIC ELECTRONIC COMPONENT

Non-Final OA §102§103
Filed
Jan 13, 2025
Priority
Mar 19, 2024 — JP 2024-043772
Examiner
DOLE, TIMOTHY J
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
207 granted / 278 resolved
+14.5% vs TC avg
Moderate +8% lift
Without
With
+8.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
7 currently pending
Career history
288
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
47.2%
+7.2% vs TC avg
§102
35.2%
-4.8% vs TC avg
§112
10.5%
-29.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 278 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections Claim 6 is objected to because of the following informalities: “rounded rides” should be “rounded ridges” in claim 6, line 2. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 4, 5, 7-16 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishibayashi et al. (US 2020/0312562). Regarding claim 1, Nishibayashi discloses a multilayer ceramic electronic component comprising: a multilayer body (fig. 1A) including a plurality of laminated ceramic layers (fig. 1A (1a)) and a plurality of laminated internal conductive layers (fig. 1B (2) and (3), see also paragraph [0022]), a first main surface and a second main surface opposed to each other in a height direction (fig. 1A, (1M) paragraph [0022]), a first lateral surface and a second lateral surface opposed to each other in a width direction (fig. 1A, (1S) paragraph [0022]) orthogonal or substantially orthogonal to the height direction, and a first end surface and a second end surface opposed to each other in a length direction (fig. 1A (1E) paragraph [0022]) orthogonal or substantially orthogonal to the height direction and the width direction; a first external electrode (fig. 1A (4)) on the first end surface; and a second external electrode (fig. 1A (5)) on the second end surface; the multilayer body including: an inner layer portion including the plurality of laminated ceramic layers and the plurality of laminated internal conductive layers (fig. 2, portion from top conductive layer 2 to bottom conductive layer 3); and a first outer layer portion (fig. 2, ceramic portion above top conductive layer 2) and a second outer layer portion (fig. 2, ceramic potion below bottom conductive layer 3) sandwiching the inner layer portion in the height direction (fig. 2); and the first external electrode and the second external electrode each including: an end surface-side base electrode layer (fig. 2 (6)); an end surface-side electrically conductive resin layer (fig. 2 (7) and paragraph [0030]) on the end surface-side base electrode layer (fig. 2); and an end surface-side plated layer (fig. 2 (8)) on the end surface-side electrically conductive resin layer (fig. 2); wherein the end surface-side base electrode layer includes an intermittent region in which the end surface-side base electrode layer is intermittently present at least in a region of the inner layer portion in a vicinity of the first outer layer portion and a region of the inner layer portion in a vicinity of the second outer layer portion (fig. 2 and [0029]); and in a region in which the end surface-side base electrode layer is interrupted, the end surface-side electrically conductive resin layer is in contact with a corresponding one of the plurality of laminated ceramic layers and a corresponding one of end portions of the plurality of laminated internal conductive layers (fig. 2, note conductive resin layer 7 contacts both the ceramic layers and the conductive layers). Regarding claim 2, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein the end surface-side electrically conductive resin layer includes a filler in contact with a corresponding one of the end portions of the plurality of laminated internal conductive layers (fig. 2 see portions of conductive resin 7 in contact with conductive layers 2 and 3, also paragraph [0030] disclosing a silver filler, Ag). Regarding claim 4, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein the intermittent region extends from the inner layer portion across the first outer layer portion and from the inner layer portion across the second outer layer portion (fig. 2); and in the region in which the end surface-side base electrode layer is interrupted, the end surface-side electrically conductive resin layer is in contact with the first outer layer portion or the second outer layer portion (fig. 2). Regarding claim 5, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein the multilayer body has a substantially rectangular parallelepiped shape (fig. 1A). Regarding claim 7, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein each of the plurality of ceramic layers is made of a dielectric material (paragraph [0023]). Regarding claim 8, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein the end surface-side plated layer of each of the first and second external electrodes includes a Ni plated layer and an Sn plated layer (paragraph [0031]). Regarding claim 9, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein a configuration of layers of the first external electrode and the second external electrode are the same or substantially the same (fig. 2). Regarding claim 10, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein the first external electrode and the second external electrode are substantially plane symmetrical with respect to a length-width cross section in a middle of the length direction of the multilayer body (figs. 1A and 2). Regarding claim 11, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein the end surface-side base electrode layer of each of the first and second external electrode is a fired layer (paragraph [0062]). Regarding claim 12, Nishibayashi discloses the multilayer ceramic electronic component according to claim 11, wherein the fired layer includes a metal component and either or both of a glass component and a ceramic component (paragraph [0028]). Regarding claim 13, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein a thickness in the length direction of the end surface-side base electrode layer of each of the first and second external electrode is about 2 μm or more and about 220 μm or less in a middle portion in the lamination direction and the width direction (paragraph [0053] - wherein the capacitor is 1 mm in length, and paragraph [0066] - wherein the thickness of external electrode base layer 6 is 1/40 of the length, or 25 μm). Regarding claim 14, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein a thickness in the length direction of the end surface-side base electrode layer of each of the first and second external electrode is about 10 μm or more and about 45 μm or less in a middle portion in the lamination direction and the width direction (paragraph [0053] - wherein the capacitor is 1 mm in length, and paragraph [0066] - wherein the thickness of external electrode base layer 6 is 1/40 of the length, or 25 μm). Regarding claim 15, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein a thickness in the length direction of the end surface-side electrically conductive resin layer of each of the first and second external electrodes is about 10 μm or more and about 200 μm or less in a middle portion in the lamination direction and the width direction (paragraph [0053] - wherein the capacitor is 1 mm in length, and paragraph [0066] - wherein the thickness of external electrode base layer 6 is 1/40 of the length, or 25 μm, and paragraph [0064] - wherein the resin layer is 50% of the thickness of the base layer 6, or 25 μm/2 = 12.5 μm). Regarding claim 16, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein the intermittent region includes a plurality of interruption regions in which an end surface is exposed at the end surface-side electrically conductive resin layer (fig. 2). Regarding claim 19, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, wherein the region of the inner layer portion in the vicinity of the first outer layer portion and the region of the inner layer portion in the vicinity of the second outer layer portion range from a boundary between the inner layer portion and the outer layer portion to a position at about 5% of a dimension of the inner layer portion in the lamination direction toward a middle of the inner layer portion in the height direction (fig. 2, note the claimed region, while not explicitly mentioned, does exist in the reference since the intermittent region occurs along the whole end surface). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 3, 6 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishibayashi et al. (US 2020/0312562) in view of Take et al. (US 2023/0245832). Regarding claim 3, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, except wherein the end surface-side base electrode layer includes an anchor portion located in a portion adjacent to the region in which the end surface-side base electrode layer is interrupted and extending in a direction away from one of the first end surface or the second end surface in the length direction, and bending toward the end surface; and the end surface-side electrically conductive resin layer includes a portion between the anchor portion and one of the first end surface or the second end surface. Take discloses a multilayer ceramic electronic component (fig. 1), wherein the end surface-side base electrode layer (fig. 12B (21)) includes an anchor portion located in a portion adjacent to the region in which the end surface-side base electrode layer is interrupted (fig. 12B) and extending in a direction away from one of the first end surface or the second end surface in the length direction (fig. 12B), and bending toward the end surface (fig. 12B, and paragraphs [0069] and [0076]); and the end surface-side electrically conductive resin layer includes a portion between the anchor portion and one of the first end surface or the second end surface (fig. 12B, and paragraphs [0069] and [0076], note Nishibayashi discloses the conductive resin later on the base layer, so the combination of using the anchor shape of Take in the base electrode layer of Nishibayashi would result in the conductive resin layer being between the anchor portion and the respective end surface). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claim invention, to use the anchor shape of Take with the base electrode layer of Nishibayashi, for the purpose of suppressing peeling of the interface between the base electrode layer and the conductive resin layer (Take: paragraph [0069]). Regarding claim 6, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, except wherein the multilayer body explicitly includes rounded ridges and corner portions (note the prior art figure 9 shows rounded corner portions, but the specification does not mention this feature). Take discloses the multilayer body includes rounded ridges and corner portions (fig. 2 shows rounded corner portions, and Fig. 3 shows rounded ridge portions). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claim invention, to use the rounded ridge and corner portions of Take with the capacitor body of Nishibayashi, for the purpose of providing better external electrode connections, reducing electrode peeling and reducing component chipping and cracking. Regarding claim 20, Nishibayashi as modified discloses the multilayer ceramic electronic component according to claim 3, wherein the anchor portion includes an undercut portion (Take: fig. 12B). Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishibayashi et al. (US 2020/0312562) in view of Ando (US 2017/0098505). Regarding claim 17, Nishibayashi discloses the multilayer ceramic electronic component according to claim 16, except wherein a ratio of the presence of the interruption regions increases toward the first or second outer layer portions. Ando discloses a multilayer ceramic capacitor (figs. 1 and 2) wherein a ratio of the presence of the interruption regions increases toward the first or second outer layer portions (fig. 7, see exposed portions in regions 21c, increasing towards outer layer portions). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claim invention, to use the external electrode configuration of Ando with the invention of Nishibayashi, for the purpose of improving fixing strength between the body and external electrode while maintaining electrical contact and relaxing stress (paragraph [0003]). Regarding claim 18, Nishibayashi discloses the multilayer ceramic electronic component according to claim 1, except wherein the intermittent region is not provided in a middle region in the height direction of the inner layer portion. Ando discloses the intermittent region is not provided in a middle region in the height direction of the inner layer portion (figs. 4 and 7). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claim invention, to use the external electrode configuration of Ando with the invention of Nishibayashi, for the purpose of improving fixing strength between the body and external electrode while maintaining electrical contact and relaxing stress (paragraph [0003]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Timothy J Dole whose telephone number is (571)272-2229. The examiner can normally be reached M-F 6:30am-2:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Wellington can be reached at (571)272-4483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jan 13, 2025
Application Filed
Aug 13, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
83%
With Interview (+8.1%)
2y 8m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 278 resolved cases by this examiner. Grant probability derived from career allowance rate.

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