The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
Claims 1-20 are rejected on the ground of no statutory double patenting as being unpatentable over claims 1-20 of patent application 12197266. The table listed below shows the similarity between the two and highlight the differences.
Instant Application 19018748
Patent 12197266
An apparatus comprising:
a set of memory devices, including a first subset of one or more memory devices and a second subset of one or more memory devices that is disjoint from the first subset; and
a memory management circuitry configured to:
translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode; and
translate virtual addresses using a second interleaving pattern when operating in a second mode,
wherein the first interleaving pattern and the second interleaving pattern both map virtual addresses in a first range exclusively to memory devices in the first subset,
wherein the first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset, and
wherein the second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset.
(Currently Amended) An apparatus comprising:
a set of memory devices, including a first subset of one or more memory devices and a second subset of one or more memory devices that is disjoint from the first subset; and
a memory management circuitry configured to:
translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode;
translate virtual addresses using a second interleaving pattern when operating in a second mode; and
power down a memory device in the set of memory devices when using the second interleaving pattern,
wherein the first interleaving pattern is a first memory map and the second interleaving pattern is a second memory map,
wherein the first interleaving pattern and the second interleaving pattern both map virtual addresses in a first range exclusively to memory devices in the first subset,
wherein the first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset, and
wherein the second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset.
2. The apparatus of claim 1, comprising: a power conservation circuitry configured to power down memory devices in the second subset while the memory management circuitry is operating in the second mode.
3. The apparatus of claim 2, wherein the power conservation circuitry powers down the memory devices in the second subset by changing a voltage on an enable conductor of the memory devices in the second subset.
4. The apparatus of claim 2, wherein the power conservation circuitry powers down the memory devices in the second subset by gating a clock signal into the memory devices in the second subset.
5. The apparatus of claim 1, wherein the memory management circuitry is configured to dynamically change between the first mode and the second mode without rebooting a processing apparatus running software stored in the set of memory devices.
6. The apparatus of claim 1, wherein the first interleaving pattern maps virtual addresses in a third range exclusively to memory devices in the second subset, and the second interleaving pattern maps virtual addresses in the third range to a memory fault.
7. The apparatus of claim 6, wherein the first interleaving pattern maps virtual addresses in a fourth range to memory devices in the first subset and in the second subset, and the second interleaving pattern maps virtual addresses in the fourth range to a memory fault.
8. The apparatus of claim 1, further comprising: a non-volatile memory storing software that is configured to store heap data at virtual addresses in the second range.
9. The apparatus of claim 1, further comprising: a non-volatile memory storing software that is configured to store operating system code at virtual addresses in the first range.
10. The apparatus of claim 1, wherein each memory device in the set of memory devices is a memory bank that can be accessed in parallel with other memory banks in the set of memory devices.
11. The apparatus of claim 1, wherein a memory device in the set of memory devices is a double data rate synchronous dynamic random access memory chip.
12. The apparatus of claim 1, wherein the memory management circuitry is configured to, when operating in the second mode, return a memory fault for virtual addresses outside of the first range and the second range.
13. The apparatus of claim 1, wherein the first interleaving pattern uses a 512-byte page size with consecutive pages in virtual memory mapped to different memory devices of the set of memory devices.
2. (Original) The apparatus of claim 1, comprising: a power conservation circuitry configured to power down memory devices in the second subset while the memory management circuitry is operating in the second mode.
3. (Original) The apparatus of claim 2, wherein the power conservation circuitry powers down the memory devices in the second subset by changing a voltage on an enable conductor of the memory devices in the second subset.
4. (Original) The apparatus of claim 2, wherein the power conservation circuitry powers down the memory devices in the second subset by gating a clock signal into the memory devices in the second subset.
5. (Original) The apparatus of claim 1, wherein the memory management circuitry is configured to dynamically change between the first mode and the second mode without rebooting a processing apparatus running software stored in the set of memory devices.
6. (Original) The apparatus of claim 1, wherein the first interleaving pattern maps virtual addresses in a third range exclusively to memory devices in the second subset, and the second interleaving pattern maps virtual addresses in the third range to a memory fault.
7. (Original) The apparatus of claim 6, wherein the first interleaving pattern maps virtual addresses in a fourth range to memory devices in the first subset and in the second subset, and the second interleaving pattern maps virtual addresses in the fourth range to a memory fault.
8. (Original) The apparatus of claim 1, further comprising: a non-volatile memory storing software that is configured to store heap data at virtual addresses in the second range.
9. (Original) The apparatus of claim 1, further comprising: a non-volatile memory storing software that is configured to store operating system code at virtual addresses in the first range.
10. (Original) The apparatus of claim 1, wherein each memory device in the set of memory devices is a memory bank that can be accessed in parallel with other memory banks in the set of memory devices.
11. (Original) The apparatus of claim 1, wherein a memory device in the set of memory devices is a double data rate synchronous dynamic random access memory chip.
12. (Original) The apparatus of claim 1, wherein the memory management circuitry is configured to, when operating in the second mode, return a memory fault for virtual addresses outside of the first range and the second range.
13. (Original) The apparatus of claim 1, wherein the first interleaving pattern uses a 512-byte page size with consecutive pages in virtual memory mapped to different memory devices of the set of memory devices.
As shown from the table above, claims 1-13 of patent 12197266 teach the same concept of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 10, 12-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chun (US Patent Application 20170108911) in the view of Desai (US Patent Application 20190361807).
As per claim 1, Chun teaches an apparatus [100, fig. 1] comprising:
a set of memory devices [110, 118, fig. 1], including a first subset [110, fig. 1] of one or more memory devices and a second subset [118, fig. 1] of one or more memory devices that is disjoint from the first subset [0034, as shown in figure 1, computing system 100 includes memory 110 and memory 118 where memory 11 includes multiple memories such as 112 and 114 and memory 118 includes multiple memories such as memory 12 and 122].
Chun does not teach a memory management circuitry configured to: translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode; and translate virtual addresses using a second interleaving pattern when operating in a second mode, wherein the first interleaving pattern and the second interleaving pattern both map virtual addresses in a first range exclusively to memory devices in the first subset, wherein the first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset, and wherein the second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset.
However, Desai teaches a memory management circuitry [120, fig. 2] configured to: translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode [0049-0050, fig.7 as shown in figure 7 and explained from the listed paragraph, the memory management performs address translation where the interleaving is manipulating in order to manage power consumption. For example, illustrate the potential power/energy savings of using dynamic adjustment of memory channel interleave granularity, another example will be described with reference to FIGS. 6 and 7 in which a memory transaction involves a relatively small chunk of data].
and translate virtual addresses using a second interleaving pattern when operating in a second mode mode [0049-0050, fig.7 as shown in figure 7 and explained from the listed paragraph, the memory management performs address translation where the interleaving is manipulating in order to manage power consumption. For example, illustrate the potential power/energy savings of using dynamic adjustment of memory channel interleave granularity, another example will be described with reference to FIGS. 6 and 7 in which a memory transaction involves a relatively small chunk of data].
wherein the first interleaving pattern and the second interleaving pattern both map virtual addresses in a first range exclusively to memory devices in the first subset [0030, the memory management performs address translation mapping for specific memory, for example, in general, the SoC processing devices 114, 116, and 118 may be configured to perform processing operations with reference to virtual memory addresses. MMUs 120, 122, and 124 translate virtual memory addresses used by the SoC processing device 114, 116, and 118, respectively, into physical memory addresses used by the system memory (e.g., DDR memory 104) with reference to page tables that are stored in the system memory. MMUs 120, 122, and 124 comprise logic (e.g., hardware, software, or a combination thereof) for performing address translation for the corresponding SoC processing device. As known in the art, MMUs 120, 122, and 124 may comprise a corresponding translation buffer unit (TBU) and a translation control unit (TCU)].
wherein the first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset [0030, the memory management performs address translation mapping for specific memory, for example, in general, the SoC processing devices 114, 116, and 118 may be configured to perform processing operations with reference to virtual memory addresses. MMUs 120, 122, and 124 translate virtual memory addresses used by the SoC processing device 114, 116, and 118, respectively, into physical memory addresses used by the system memory (e.g., DDR memory 104) with reference to page tables that are stored in the system memory. MMUs 120, 122, and 124 comprise logic (e.g., hardware, software, or a combination thereof) for performing address translation for the corresponding SoC processing device. As known in the art, MMUs 120, 122, and 124 may comprise a corresponding translation buffer unit (TBU) and a translation control unit (TCU)].
wherein the second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset [0020, as pointed out the mapping can be complex or not complex as indicated. For example, a translation or mapping may be used to convert a virtual memory address to a physical memory address. The mapping may be as simple as 1-to-1 (e.g., physical address equals virtual address), moderately complex (e.g., a physical address equals a constant offset from the virtual address), or the mapping may be complex (e.g., every 4 KB page mapped uniquely). The mapping may be static (e.g., performed once at startup), or the mapping may be dynamic (e.g., continuously evolving as memory is allocated and freed)].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify to modify Chun to include the method Desai in order to perform dynamic memory interleave patter to help manage power consumption.
As per claim 14, Chun teaches a method [300, fig. 3] comprising:
executing instructions of operating system software for a processing apparatus stored in one or more memory devices in a set of memory devices using a first interleaving pattern to map virtual addresses to physical addresses [0030, 0040, 0042, fig. fig. 3 and fig. 4A, as pointed and shown in the listed paragraphs, the memory management unit 103 translates virtual address to physical address mapping using interleave and linear where a first operating mode is a mode that correspond to a high performance mode and a second operating mode is a mode that correspond to a lower performance mode. As pointed out in paragraphs 0036-0037, the overall process is performed by an operating system and executed by the processor of the computing system].
executing instructions of the operating system software using the second interleaving pattern, wherein the first interleaving pattern uses all memory devices in the set of memory devices and the second interleaving pattern uses less than all of the memory devices in the set of memory devices [0068, 0071, fig. 16, fig. 18 as pointed out specific memory address range can be used for either linear or interleave where all can be used or less than specific memory addresses].
Chun does not teach invoking a change from a first mode to a second mode for the processing apparatus while continuing to execute the operating system software, wherein the processing apparatus uses the first interleaving pattern for virtual address translation when in the first mode and uses a second interleaving pattern for virtual address translation when in the second mode,
However, Desai teaches invoking a change from a first mode to a second mode for the processing apparatus while continuing to execute the operating system software, wherein the processing apparatus uses the first interleaving pattern for virtual address translation when in the first mode and uses a second interleaving pattern for virtual address translation when in the second mode [0027, as pointed out various granularity interleave patter can be selected for example 256 byte or 512 byte or 1 kilobyte or 2kylobyte and so forth. In this case, the granularity interleaves can be selected depending on performance requirement. For example, exemplary embodiment, the predefined interleave granularities are selected from boundary or granularity values of 256 B, 512 B, 1 kB, and 2 kB. As mentioned above, conventional channel interleaving is applied at a fixed sized boundary without regard to performance requirements, bandwidth requirements, memory data access sizes, etc. For example, many high-tier SoCs comprise eight DDR channels with a 256 B fixed interleave granularity. While a 256 B interleave granularity may advantageously meet the demands of certain high-performance masters (e.g., CPUs, GPUs) and efficiently balance traffic across all DDR channels, not all of the SoC processing devices and/or use cases implemented in system 100 may require this level of performance].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify to modify Chun to include the method Desai to dynamically adjust the interleaves patter in order to manage power consumption.
As per claim 6, Chun teaches the first interleaving pattern maps virtual addresses in a third range exclusively to memory devices in the second subset, and the second interleaving pattern maps virtual addresses in the third range to a memory fault [0042, 0044, fig. 4-6, as pointed out the mapping can be done on specific address range disregard the pattern usage].
As per claim 7, Chun teaches the first interleaving pattern maps virtual addresses in a fourth range to memory devices in the first subset and in the second subset, and the second interleaving pattern maps virtual addresses in the fourth range to a memory fault [0042, 0044, fig. 4-6, as pointed out the mapping can be done on specific address range disregard the pattern usage].
As per claim 10, Chun teaches each memory device in the set of memory devices is a memory bank that can be accessed in parallel with other memory banks in the set of memory devices [fig. 4-6 shows that memory address can be accessed in parallel].
As per claim 12, Chun teaches the memory management circuitry is configured to, when operating in the second mode, return a memory fault for virtual addresses outside of the first range and the second range [0044, 0060 fig. 4, fig. 13, process is done until the tope address is reached and continue].
As per claim 13, Chun teaches the first interleaving pattern uses a 512-byte page size with consecutive pages in virtual memory mapped to different memory devices of the set of memory devices [0041, fixed size like 512 bytes].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5, 8, 9, 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chun (US Patent Application 20170108911) in the view of Haas Costa (US Patent Application 20180225059).
As per claim 2, Chun does not teach a power conservation circuitry configured to power down memory devices in the second subset while the memory management circuitry is operating in the second mode.
However, Haas Costa teaches a power conservation circuitry configured to power down memory devices in the second subset while the memory management circuitry is operating in the second mode [0053, 0074, power down section of the volatile memory as pointed out].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design Chun to include the method of Hass Costa to power down portion of the memory based on operating mode.
As per claim 5, Chun does not teach the memory management circuitry is configured to dynamically change between the first mode and the second mode without rebooting a processing apparatus running software stored in the set of memory devices.
However, Haas Costa teaches the memory management circuitry is configured to dynamically change between the first mode and the second mode without rebooting a processing apparatus running software stored in the set of memory devices [0050, as pointed out the mapping can be done by the operating system where the system does not have to reboot].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design Chun to include the method of Hass Costa to perform the mapping of the memory address not when booting or during the booting phase.
As per claim 8, Chun does not teach a non-volatile memory storing software that is configured to store heap data at virtual addresses in the second range.
However, Haas Costa teaches a non-volatile memory storing software that is configured to store heap data at virtual addresses in the second range [0022, 0028, 0034 nonvolatile memory for storing data].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design Chun to include the method of Hass Costa to use nonvolatile memory to store the data.
As per claim 9, Chun does not teach a non-volatile memory storing software that is configured to store operating system code at virtual addresses in the first range.
However, Haas Costa teaches a non-volatile memory storing software that is configured to store operating system code at virtual addresses in the first range [0030, operating system code in nonvolatile memory].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design Chun to include the method of Hass Costa to use nonvolatile memory to store the operating system code.
As per claim 11, Chun does not teach a memory device in the set of memory devices is a double data rate synchronous dynamic random access memory chip.
However, Haas Costa teaches a memory device in the set of memory devices is a double data rate synchronous dynamic random access memory chip [0017, the memory can be the type of SDRAM and other memory type].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design Chun to include the method of Hass Costa to use other types of memory such as SDRAM.
As per claims 14-20, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 14-2 are also rejected as being unpatentable over Chun in view of Haas Costa for the same reasons set forth in the rejected claims above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Desai (US 20190306005) teaches bandwidth-based selective memory channel connectivity on a system on chip.
Cypher (US 20100325374) teaches dynamically configuring memory intelligence for locality and performance isolation.
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2187
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