DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1, 4, 8, 9, 12, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al. (US 2019/0324856), “Zhao”.
2. As per claim 1, Zhao discloses one or more processors [figure 6] configured to: in response to receiving a checkpoint signal, determine a location of related data of an application in a memory region [in order to perform a checkpoint operation, locating an intermediate DL model residing in a server node, abstract]; based on the location of the related data in the memory region [an intermediated DL model residing in a server node, abstract], perform a checkpointing operation on the related data using either one or both of a host processor and an accelerator processor [performing a checkpoint operation on the intermediate DL mode using a CPU, paragraph 45]; and compress the related data using the either one or both of the host processor and the accelerator processor that has performed the checkpointing operation [compressing the intermediate DL model using the CPU, paragraph 45], wherein the location of the related data in the memory region comprises a location in either one or both of a host memory region and an accelerator memory region [an intermediated DL model residing with accelerator devices in a server node, abstract].
3. As per claim 4, Zhao discloses wherein, for the compressing, the one or more processors are configured to: in response to performing the checkpointing operation using the accelerator processor on data located in the accelerator memory region of the related data [the checkpoint optimization module function executed in a host processor or an accelerator device, paragraph 35], determine a size and a distribution characteristic of the data located in the accelerator memory region [checkpointing in a “disturbed environment” for the data size of 500 MB or greater residing in a GPU device memory, paragraph 5]; and compress the data located in the accelerator memory region based on the determined size and the determined distribution characteristic [compressing the intermediate DL model residing with accelerator devices in the server node, paragraph 45, abstract].
4. As per claim 8, Zhao discloses wherein for the performing of the checkpointing operation, the one or more processors are configured to perform the checkpointing operation [the checkpoint optimization module function executed in a host processor or an accelerator device, paragraph 35] in parallel [parallel GPU devices 762, figure 7], and respective files generated by the checkpointing operation performed in parallel are independent of each other [such parallel GPU devices operating independent of each other, figure 7].
5. As per claim 9, Zhao discloses receiving a checkpoint signal [step 502, figure 5]; in response to receiving the checkpoint signal, determining a location of related data of an application in a memory region [in order to perform a checkpoint operation, locating an intermediate DL model residing in a server node, abstract]; based on the location of the related data in the memory region, performing a checkpointing operation on the related data using either one or both of a host processor and an accelerator processor [performing a checkpoint operation on the intermediate DL mode using a CPU, paragraph 45]; and compressing the related data using the either one or both of the host processor and the accelerator processor that has performed the checkpointing operation [compressing the intermediate DL model using the CPU, paragraph 45], wherein the location of the related data in the memory region comprises a location in either one or both of a host memory region and an accelerator memory region [an intermediated DL model residing with accelerator devices in a server node, abstract].
6. As per claim 12, Zhao discloses wherein the compressing comprises: in response to performing the checkpointing operation using the accelerator processor on data located in the accelerator memory region of the related data [the checkpoint optimization module function executed in a host processor or an accelerator device, paragraph 35], determining a size and a distribution characteristic of the data located in the accelerator memory region [checkpointing in a “disturbed environment” for the data size of 500 MB or greater residing in a GPU device memory, paragraph 5]; and compressing the data located in the accelerator memory region based on the determined size and the determined distribution characteristic [compressing the intermediate DL model residing with accelerator devices in the server node, paragraph 45, abstract].
7. As per claim 16, Zhao discloses wherein the performing of the checkpointing operation comprises performing the checkpointing operation [the checkpoint optimization module function executed in a host processor or an accelerator device, paragraph 35] in parallel [parallel GPU devices 762, figure 7], and respective files generated by the checkpointing operation performed in parallel are independent of each other [such parallel GPU devices operating independent of each other, figure 7].
8. As per claim 17, Zhao discloses A non-transitory computer-readable storage medium storing instructions [an article of manufacture embodiment, claim 10] that, when executed by one or more processors, configure the one or more processors to perform the method of claim 9.
9. As per claim 18, Zhao discloses one or more processors [figure 6] configured to: based on a location of related data of an application in a memory region [an intermediated DL model residing in a server node, abstract], determining whether to perform a checkpointing operation on the related data using either one of a host processor and an accelerator processor [performing a checkpoint operation on the intermediate DL mode using a CPU, paragraph 45]; and in response to determining to perform the checkpointing operation using the accelerator processor on data located in an accelerator memory region of the related data [the checkpoint optimization module function executed in a host processor or an accelerator device, paragraph 35], determine a size and a distribution characteristic of the data located in the accelerator memory region [checkpointing in a “disturbed environment” for the data size of 500 MB or greater residing in a GPU device memory, paragraph 5]; and compress the data located in the accelerator memory region based on the determined size and the determined distribution characteristic [compressing the intermediate DL model residing with accelerator devices in the server node, paragraph 45, abstract].
Conclusion
A. Allowable Subject Matter
Claims 2, 3, 5-7, 10, 11, 13-15, and 19 are objected to.
The closest prior art of record, “Zhao” discloses data compression using processing units.
The primary reasons for allowance of claim 2 in the instant application is the combination with the inclusion in these claims that “wherein, for the performing of the checkpointing operation, the one or more processors are configured to: in response to first partial data of the related data being in the host memory region, determine a first overhead for performing the checkpointing operation on the first partial data using the host processor; determine a second overhead for performing the checkpointing operation on the first partial data using the accelerator processor; perform the checkpointing operation on the first partial data using a processor corresponding to a smaller one between the first overhead and the second overhead; and in response to second partial data of the related data being in the accelerator memory region, perform the checkpointing operation on the second partial data using the accelerator processor”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 5 in the instant application is the combination with the inclusion in these claims that “wherein, for the compressing, the one or more processors are configured to: in response to the determined size of the data located in the accelerator memory region being greater than a first threshold value, and in response to the determined distribution characteristic indicating that the data located in the accelerator memory region is stored successively, partition the data located in the accelerator memory region into a plurality of data blocks based on a second threshold value greater than the first threshold value; and compress each of the plurality of data blocks using the accelerator processor”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 6 in the instant application is the combination with the inclusion in these claims that “wherein the data located in the accelerator memory region comprises a plurality of data blocks, for the compressing, the one or more processors are configured to: in response to the distribution characteristic indicating that storage locations of the plurality of data blocks are proximate to each other, merge the plurality of data blocks; and compress the plurality of data blocks using the accelerator processor, and the plurality of data blocks has a size less than a third threshold value”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 7 in the instant application is the combination with the inclusion in these claims that “wherein the data located in the accelerator memory region comprises a plurality of data blocks, and for the compressing, the one or more processors are configured to: in response to the distribution characteristic indicating that the plurality of data blocks is sparsely distributed, partition the plurality of data blocks into a plurality of groups; assign a plurality of streams to each of the plurality of groups; and compress the data located in the accelerator memory region based on the accelerator processor and the plurality of streams”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 10 in the instant application is the combination with the inclusion in these claims that “wherein the performing of the checkpointing operation comprises: in response to first partial data of the related data being in the host memory region, determining a first overhead for performing the checkpointing operation on the first partial data using the host processor; determining a second overhead for performing the checkpointing operation on the first partial data using the accelerator processor; performing the checkpointing operation on the first partial data using a processor corresponding to a smaller one between the first overhead and the second overhead; and in response to second partial data of the related data being in the accelerator memory region, performing the checkpointing operation on the second partial data using the accelerator processor”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 13 in the instant application is the combination with the inclusion in these claims that “wherein the compressing comprises: in response to the determined size of the data located in the accelerator memory region being greater than a first threshold value, and in response to the determined distribution characteristic indicating that the data located in the accelerator memory region is stored successively, partitioning the data located in the accelerator memory region into a plurality of data blocks based on a second threshold value greater than the first threshold value; and compressing each of the plurality of data blocks using the accelerator processor”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 14 in the instant application is the combination with the inclusion in these claims that “wherein the compressing comprises: in response to the data comprising a plurality of data blocks, and in response to the distribution characteristic indicating that storage locations of the plurality of data blocks are proximate to each other, merging the plurality of data blocks; and compressing the plurality of data blocks using the accelerator processor, and the plurality of data blocks has a size less than a third threshold value”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 15 in the instant application is the combination with the inclusion in these claims that “wherein the data located in the accelerator memory region comprises a plurality of data blocks, and the compressing comprises: in response to the distribution characteristic indicating that the plurality of data blocks is sparsely distributed, partitioning the plurality of data blocks into a plurality of groups; assigning a plurality of streams to each of the plurality of groups; and compressing the data located in the accelerator memory region based on the accelerator processor and the plurality of streams”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 19 in the instant application is the combination with the inclusion in these claims that “wherein, for the compressing, the one or more processors are configured to based on the determined size and the determined distribution characteristic, perform any one of: partitioning the data located in the accelerator memory region into a plurality of data blocks; merging the plurality of data blocks; and assigning a plurality of streams to each of a plurality of groups into which the plurality of data blocks are partitioned; and compress the data located in the accelerator memory region based on a result of the any one of the partitioning of the data, the merging of the plurality of data blocks, and the assigning of the plurality of streams”. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's response must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 C.F.R. § 1.111(b) and § 707.07(a) of the MPEP.
B. Claims Rejected
Claims 1, 4, 8, 9, 12, and 16-18 are rejected.
C. Direction of Future Remarks
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/JAE U YU/Primary Examiner, Art Unit 2138