Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 01/13/2025. Claims 1-20 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mendel U.S. patent No. 9,942,063.
Fig. 1B of Mendel discloses an apparatus (140) comprising: a transmitter (142A) connected to a signal line (150), the transmitter (142A) including an encoder (146A; see Fig. 7) configured to: encode data bits (148A; See Fig. 4A, 4B) to be transmitted through the signal line (150), according to pulse amplitude modulation (Fig. 2A, Col. 6 lines 6-14), and convert the data bits into data symbols having multiple voltage levels (Fig. 2A), wherein the encoder (146A; Fig. 7 ) includes: a logic circuit (160 in Fig. 7) configured to provide look-up tables (Col. 12 lines 50-53) indicating a correlation (Col. 12 lines 21-27) between the data bits and the data symbols (Fig. 4A and Fig. 4B), the look-up tables (Col. 12 lines 50-53) including mappings (Fig. 5; Col. 12 lines 36-34)related to operation requirements of the encoder (146A), the operation requirements of the encoder (146A) including a direct current (DC) balance requirement and a run-length limit (Col. 16 lines 53-54) requirement of the data symbols (Fig. 4A and Fig. 4B) and a control circuit (182) configured to selectively control logic operations (operation of 160 in Fig. 7) of the logic
Allowable Subject Matter
5. Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach wherein: the logic circuit is configured to map 8-bit user data included in the data bits to four data symbols, generate 256 patterns by performing level encoding of upper two symbols and lower two symbols among the four data symbols, and provide a first look-up table including five data symbols by adding one edge symbol having symbol level 1 or 2 to the end of the 256 patterns, and the multiple voltage levels includes an uppermost level having symbol level 3, a lowermost level having symbol level 0, the symbol level 1 having a voltage level higher than a voltage level of the symbol level 0, and the symbol level 2 having a voltage level higher than the voltage level of the symbol level 1 and lower than a voltage level of the symbol level 3.
6. Claims 12-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 12, in addition to other elements in the claim, prior art considered individual or combination does not teach: output an RD flag symbol based on the calculated RD value, the transmitter is configured to sequentially output the first packet, the RD flag symbol, and the second packet through the signal line, and the encoder is configured to determine whether to perform an operation of inverting the data symbols of the second packet according to the RD flag symbol.
With respect to claim 15, in addition to other elements in the claim, prior art considered individual or combination does not teac: look-up tables including mappings relating to requirements of the PAM encoding, the PAM encoding requirements including a maximum transition avoidance (MTA) requirement of avoiding a maximum transition (MT) event between the data symbols and a direct current (DC) balance requirement and a run-length limit requirement of the data symbols; remapping codes in a look-up table satisfying the requirements of the PAM encoding, among the look-up tables, to bit encoding patterns of the first set of data bits; and transmitting a remapped code corresponding to the first set of data bits through the signal line.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Contact Information
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
07/30/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
Prosecution Insights