DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on January 13, 2025. These drawings are acceptable.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN Publication 105206424 to Qiao (see also provided machine translation).
Claim 1
Qiao (FIG. 1) discloses a multilayer ceramic electronic component, comprising:
a multilayer body (2) that includes a plurality of ceramic layers (4) and a plurality of inner conductive layers (1) stacked alternately in a height direction, a first main surface (bottom) and a second main surface (top) on opposite sides in the height direction, a first end surface (left end surface) and a second end surface (right end surface) on opposite sides in a length direction orthogonal or substantially orthogonal to the height direction, and a first lateral surface (first side surface) and a second lateral surface (second side surface) on opposite sides in a width direction orthogonal or substantially orthogonal to both the height direction and the length direction; and
a pair of external electrodes (3) spaced apart from each other at both end portions of the multilayer body (2) in the length direction; wherein
the plurality of inner conductive layers (1) include:
a first inner conductive layer (1) extending to the first end surface (left end surface); and
a second inner conductive layer (1) extending to the second end surface (right end surface);
the pair of external electrodes (3) include:
a main surface-side external electrode (3) on at least one of the first main surface (bottom) or the second main surface (top);
the main surface-side external electrode (3) includes:
a main surface-side base electrode layer (5);
a main surface-side conductive resin layer (6) above the main surface-side base electrode layer (5); and
a main surface-side plated layer (7) above the main surface-side conductive resin layer (6); and
in a cross-sectional view along the height direction and the length direction, the main surface-side conductive resin layer (6) includes a conductive resin layer recess (11) recessed toward a side of the multilayer body (2) at a boundary interface with the main surface-side plated layer (7).
Claim 5
Qiao discloses the multilayer ceramic electronic component according to claim 1, wherein the multilayer body includes:
an inner layer portion (portion from upper 1 to lower 1 with layers 4 therebetween) including some of the plurality of ceramic layers (4) and some of the plurality of inner conductive layers (1); and
first and second main surface-side outer layer portions (uppermost 4 and lowermost 4) with the inner layer portion interposed therebetween.
Claim 10
Qiao discloses the multilayer ceramic electronic component according to claim 1, wherein each of the plurality of inner conductive layers includes Ni, Cu, Ag, Pd, or Au, or alloys including at least one of Ni, Cu, Ag, Pd, or Au (“the internal electrode is made of nickel metal”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 6-8, 11, 13-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Qiao in view of US Publication 2017/0294268 to Katsuta et al. (hereinafter Katsuta).
Claim 4
Qiao discloses the multilayer ceramic electronic component according to claim 1, wherein
a dimension of the multilayer body in the height direction is between about 0.1 mm and about 10 mm inclusive (“the thickness of the ceramic unit layer is 1~2mm”).
Qiao does not expressly disclose a dimension of the multilayer body in the length direction L is between about 0.2 mm and about 10 mm inclusive; and a dimension of the multilayer body in the width direction is between about 0.1 mm and about 10 mm inclusive, as recited in claim 4.
Katsuta (paragraph 77) teaches a dimension of a multilayer body in a length direction L is between about 0.2 mm and about 10 mm inclusive (1.6 mm); and a dimension of the multilayer body in a width direction is between about 0.1 mm and about 10 mm inclusive (0.8 mm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Qiao to incorporate dimensions of a multilayer body as taught by Katsuta in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for use of a standardized package size such as a 1608 package.
Additionally, where the only difference between the prior art and the claim is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device. See MPEP 2144.04 citing In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Claim 6
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein each of the plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component, as recited in claim 6.
Katsuta (paragraph 27) teaches wherein each of a plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Qiao to incorporate ceramic materials as taught by Katsuta in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for perovskite materials with high dielectric constants and volumetric efficiency.
Claim 7
Qiao with Katsuta teaches the multilayer ceramic electronic component according to claim 6, wherein each of the plurality of ceramic layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as an accessory component (Katsuta paragraph 27).
Claim 8
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein a thickness of each of the plurality of ceramic layers is between about 0.5 µm and about 30 µm inclusive, as recited in claim 8.
Katsuta (paragraph 27) teaches wherein a thickness of each of the plurality of ceramic layers is between about 0.5 µm and about 30 µm inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Qiao to incorporate ceramic material thickness as taught by Katsuta in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 11
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein a thickness of each of the plurality of inner conductive layers is between about 0.2 µm and about 2.0 µm inclusive, as recited in claim 11.
Katsuta (paragraph 31) teaches wherein a thickness of each of a plurality of inner conductive layers is between about 0.2 µm and about 2.0 µm inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Qiao to incorporate inner conductive layer thickness as taught by Katsuta in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 13
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein the main surface-side plated layer includes a Ni plated layer, and a Sn plated layer on the Ni plated layer, as recited in claim 13.
Katsuta (paragraph 64) teaches wherein a main surface-side plated layer includes a Ni plated layer, and a Sn plated layer on the Ni plated layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Qiao to incorporate plating layers as taught by Katsuta in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for reducing erosion of a base electrode layer when soldering while having an outermost layer of high solder wettability (Katsuta paragraph 64).
Claim 14
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein the main surface-side base electrode layer includes a metal component and at least one of a glass component and a ceramic component, as recited in claim 13.
Katsuta (paragraph 35) teaches wherein the main surface-side base electrode layer includes a metal component and at least one of a glass component and a ceramic component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Qiao to incorporate a base layer as taught by Katsuta in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for a low resistance connection to the internal electrodes while avoiding cracking from thermal expansion mismatch.
Claim 15
Qiao with Katsuta teaches the multilayer ceramic electronic component according to claim 14, wherein the metal component includes at least one of Cu, Ni, Ag, Pd, Ag-Pd alloy, or Au (Katsuta paragraph 35).
Claim 16
Qiao with Katsuta teaches the multilayer ceramic electronic component according to claim 14, wherein the glass component includes at least one of B, Si, Ba, Mg, Al, or Li (Katsuta paragraph 35).
Claim 18
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein a thickness of the main surface-side base electrode layer is between about 2 µm and about 220 µm inclusive, as recited in claim 18.
Katsuta (paragraph 35) teaches wherein a thickness of a main surface-side base electrode layer is between about 2 µm and about 220 µm inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Qiao to incorporate a base layer as taught by Katsuta in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for a low resistance connection to the internal electrodes while avoiding cracking from thermal expansion mismatch.
Claim 19
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein the main surface-side conductive resin layer includes a resin portion including resin components, and conductive filler particles dispersed within the resin portion, as recited in claim 19.
Katsuta (paragraph 53) teaches wherein a main surface-side conductive resin layer includes a resin portion including resin components, and conductive filler particles dispersed within the resin portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Qiao to incorporate conductive resin layer materials as taught by Katsuta in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for a flexible resin layer allowing for shock-absorption and avoiding generation of cracks.
Claim 20
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein a thickness of the main surface-side conductive resin layer is between about 5 µm and about 200 µm inclusive, as recited in claim 20.
Katsuta (paragraph 52) teaches wherein a thickness of a main surface-side conductive resin layer is between about 5 µm and about 200 µm inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Katsuta with Qiao to incorporate conductive resin layer thickness as taught by Katsuta in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for a flexible resin layer allowing for shock-absorption and avoiding generation of cracks.
Claims 4, 6-9, 11-12, 14-15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Qiao in view of US Publication 2022/0392709 to Nakahiro et al. (hereinafter Nakahiro).
Claim 4
Qiao discloses the multilayer ceramic electronic component according to claim 1, wherein
a dimension of the multilayer body in the height direction is between about 0.1 mm and about 10 mm inclusive (“the thickness of the ceramic unit layer is 1~2mm”).
Qiao does not expressly disclose a dimension of the multilayer body in the length direction L is between about 0.2 mm and about 10 mm inclusive; and a dimension of the multilayer body in the width direction is between about 0.1 mm and about 10 mm inclusive, as recited in claim 4.
Nakahiro (paragraph 122) teaches a dimension of a multilayer body in a length direction L is between about 0.2 mm and about 10 mm inclusive; and a dimension of the multilayer body in a width direction is between about 0.1 mm and about 10 mm inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Qiao to incorporate dimensions of a multilayer body as taught by Nakahiro in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for variation in the dimensions according to design requirements.
Additionally, where the only difference between the prior art and the claim is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device. See MPEP 2144.04 citing In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Claim 6
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein each of the plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component, as recited in claim 6.
Nakahiro (paragraph 53) teaches wherein each of a plurality of ceramic layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Qiao to incorporate ceramic materials as taught by Nakahiro in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for perovskite materials with high dielectric constants and volumetric efficiency.
Claim 7
Qiao with Nakahiro teaches the multilayer ceramic electronic component according to claim 6, wherein each of the plurality of ceramic layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as an accessory component (Nakahiro paragraph 53).
Claim 8
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein a thickness of each of the plurality of ceramic layers is between about 0.5 µm and about 30 µm inclusive, as recited in claim 8.
Nakahiro (paragraph 54) teaches wherein a thickness of each of the plurality of ceramic layers is between about 0.5 µm and about 30 µm inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Qiao to incorporate ceramic material thickness as taught by Nakahiro in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 9
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein a number of the plurality of ceramic layers is between 10 and 1500 inclusive, as recited in claim 9.
Nakahiro (paragraph 54) teaches wherein a number of the plurality of ceramic layers is between 10 and 1500 inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Qiao to incorporate a number of ceramic layers as taught by Nakahiro in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 11
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein a thickness of each of the plurality of inner conductive layers is between about 0.2 µm and about 2.0 µm inclusive, as recited in claim 11.
Nakahiro (paragraph 62) teaches wherein a thickness of each of a plurality of inner conductive layers is between about 0.2 µm and about 2.0 µm inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Qiao to incorporate inner conductive layer thickness as taught by Nakahiro in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 12
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein a number of the plurality of inner conductive layers is between 10 and 1500 inclusive, as recited in claim 12.
Nakahiro (paragraph 62) teaches wherein a number of the plurality of inner conductive layers is between 10 and 1500 inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Qiao to incorporate inner conductive layer thickness as taught by Nakahiro in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for using a high number of layers within the multilayer ceramic component, increasing capacitance.
Claim 14
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein the main surface-side base electrode layer includes a metal component and at least one of a glass component and a ceramic component, as recited in claim 13.
Nakahiro (paragraph 78) teaches wherein the main surface-side base electrode layer includes a metal component and at least one of a glass component and a ceramic component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Qiao to incorporate a base layer as taught by Nakahiro in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for a low resistance connection to the internal electrodes while avoiding cracking from thermal expansion mismatch.
Claim 15
Qiao with Nakahiro teaches the multilayer ceramic electronic component according to claim 14, wherein the metal component includes at least one of Cu, Ni, Ag, Pd, Ag-Pd alloy, or Au (Nakahiro paragraph 78).
Claim 17
Qiao with Nakahiro teaches the multilayer ceramic electronic component according to claim 14, wherein the ceramic component includes at least one of BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, or CaZrO3 (Nakahiro paragraph 79).
Claim 18
Qiao discloses the multilayer ceramic electronic component according to claim 1, as shown above.
Qiao does not expressly disclose wherein a thickness of the main surface-side base electrode layer is between about 2 µm and about 220 µm inclusive, as recited in claim 18.
Nakahiro (paragraph 85) teaches wherein a thickness of a main surface-side base electrode layer is between about 2 µm and about 220 µm inclusive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Nakahiro with Qiao to incorporate a base layer as taught by Nakahiro in the structure taught by Qiao, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for a low resistance connection to the internal electrodes while avoiding cracking from thermal expansion mismatch.
Allowable Subject Matter
Claims 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: JP Publication 2015/035589 (see, e.g., FIG. 3: recess 22a1 in baked layer 22a1; plating layer 26a1); and US Publication 2020/0082983 (see, e.g., FIG. 4: point IP in base layers 131a-b, plating layers 131c-d).
See also similar applications (but note Assignee and effective filing dates): US Publication 2025/0279240; US Publication 2025/0279242; US Publication 2025/0299883; US Publication 2025/0299884; US Publication 2025/0308794; US Publication 2026/0142086; and US Publication 2026/0260817.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN MILAKOVICH whose telephone number is (571)270-3087. The examiner can normally be reached Monday - Friday 9:00 AM - 5:00 PM EST.
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/NATHAN MILAKOVICH/Primary Examiner, Art Unit 2847
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