Detailed Action
Status of Claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claims 1-20 are rejected.
This Action is Non-Final.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/13/2025 ,the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Grosz (US Patent Application Pub. No: 20210064268 A1)in view KIM et al.(US Patent Application Pub. No: 20200233796 A1).
As per claim 1,Grosz teaches a storage device [Fig.1, memory device 110.], comprising:
at least one memory [Fig.2, a memory array (or multiple memory arrays) 201.]; and
a control unit [Fig.2, a memory control unit 218.], configured to facilitate communication between the at least one memory and a host device [Figs.1&2, … the memory device 110 can include one or more other memory devices, or the communication interface 115 can include one or more other interfaces, depending on the host 105 and the memory device 110.], and control the at least one memory, wherein the control unit includes: a memory controller configured to control an operation of the at least one memory [Figs.1& 2; Paragraphs 0031-0032, Memory device 200 can include a memory control unit 218 (which can include components such as a state machine (e.g., finite state machine), register circuits, and other components) configured to control memory operations (e.g., read, write, and erase operations) of memory device 200 based on control signals on lines 204.];
a data preservation operation manager configured to manage a data preservation operation of the at least one memory [Paragraphs 0022- 0023, Both SSDs and managed NAND devices can receive commands from a host in association with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory devices and the host, or erase operations to erase data from the memory devices.]; and
a buffer manager configured to receive a command transmitted by the host device, storing the command in a buffer memory [Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.].
Grosz does not explicitly disclose when an address associated with the command corresponds to a memory area undergoing the data preserve operation, and providing the command to the memory controller when the address does not correspond to the memory area, the memory area being included in the at least one memory.
KIM discloses when an address associated with the command corresponds to a memory area undergoing the data preserve operation, and providing the command to the memory controller when the address does not correspond to the memory area, the memory area being included in the at least one memory [Paragraphs 0039; 0047, The memory device 100 may receive a command and an address from the memory controller 200 and access an area of the memory cell array that is selected by the address. …., the memory device 100 may perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 may perform a write (program) operation, a read operation, and an erase operation.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include KIM's a method of operating a memory controller and a computing system into Grosz’s a memory device for the benefit of the storage device having an enhanced map data access performance can be realized (KIM,[0006]) to obtain the invention as specified in claim 1.
As per claim 2, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz teaches, a storage device [Grosz, Fig.1, memory device 110.], wherein, upon receiving a valid command from the buffer manager, the memory controller performs an operation of writing data to a target memory area corresponding to an address associated with the valid command [Grosz, Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.], or an operation of reading data from the target memory area, while the data preservation operation is in progress [Grosz, Paragraphs 0022- 0023, Both SSDs and managed NAND devices can receive commands from a host in association with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory devices and the host, or erase operations to erase data from the memory devices.].
As per claim 3, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz and KIM teach, a storage device, wherein the buffer manager [Grosz, Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.], provides the command stored in the buffer memory to the memory controller when the data preservation operation is complete [KIM, Paragraphs 00039;0044, ….the memory device 100 may perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 may perform a write (program) operation, a read operation, and an erase operation. During a program operation, the memory device 100 may program data to an area selected by an address.].
As per claim 4, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz teaches, a storage device, wherein the buffer manager transmits a response signal to the host device when the command is stored in the buffer memory [Grosz, Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.].
As per claim 5, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz and KIM teach, a storage device, wherein the buffer manager stores the command, the address associated with the command [Grosz, Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.], and data corresponding to the command in the buffer memory when the command is a write command [KIM, Paragraphs 0039;0047,The memory device 100 may receive a command and an address from the memory controller 200 and access an area of the memory cell array that is selected by the address].
As per claim 6, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz and KIM teach, a storage device, wherein when the command is a write command and the address associated with the command matches an address associated with a write command pre-stored in the buffer memory [Grosz, Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.], the buffer manager sets a valid flag of the command to a first value, stores the valid flag in the buffer memory, and changes a valid flag of the pre-stored write command to a second value, the first value indicating valid and the second value indicating invalid [KIM, Paragraphs 0039;0047,The memory device 100 may receive a command and an address from the memory controller 200 and access an area of the memory cell array that is selected by the address].
As per claim 7, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz and KIM teach, a storage device, wherein when the command is a write command and the address associated with the command matches an address associated with a write command pre-stored in the buffer memory [KIM, Paragraphs 0039;0047,The memory device 100 may receive a command and an address from the memory controller 200 and access an area of the memory cell array that is selected by the address], the buffer manager overwrites the pre-stored write command with the command transmitted by the host device [Grosz, Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.].
As per claim 8, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz and KIM teach, a storage device, wherein the buffer manager stores the command and the address associated [Grosz, Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.], with the command in the buffer memory when the command is a read command [KIM, Paragraphs 0096-0098, The read/write circuit 123 may include first to m-th page buffers PB1 to PBm, which may be coupled to the memory cell array 110 through the first to m-th bit lines BL1 to BLm, respectively. The first to m-th page buffers PB1 to PBm may operate under control of the control logic 130.].
As per claim 9, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz and KIM teach, a storage device, wherein when the command is a read command and the address associated [Grosz, Paragraphs 0031-0032, Memory device 200 can perform a read operation to read (e.g., sense) information (e.g., previously stored information) in memory cells 210, or a write (e.g., program) operation to store (e.g., program) information in memory cells 210.], with the command matches an address associated with a write command pre-stored in the buffer memory, the buffer manager provides data corresponding to the pre-stored write command to the host device [KIM, Paragraphs 0096-0098, The read/write circuit 123 may include first to m-th page buffers PB1 to PBm, which may be coupled to the memory cell array 110 through the first to m-th bit lines BL1 to BLm, respectively. The first to m-th page buffers PB1 to PBm may operate under control of the control logic 130.].
As per claim 10, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz teaches, a storage device, wherein when storing the command in the buffer memory, the buffer manager sets a valid flag of the command to a first value indicating valid [Grosz, Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.].
As per claim 11, Grosz and KIM teach all the limitations of claim 10 above, wherein Grosz teaches, a storage device, wherein when providing the command to the memory controller, the buffer manager changes the valid flag of the command to a second value indicating invalid [Grosz, Paragraphs 0033, 0044, Data can be received at the communication interface from the host device into buffers 526 of the memory control unit.].
As per claim 12, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz teaches, a storage device, wherein the buffer manager receives a start signal and an end signal of the data preservation operation from the data preservation operation manager [Grosz, Paragraphs 0022- 0023, Both SSDs and managed NAND devices can receive commands from a host in association with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory devices and the host, or erase operations to erase data from the memory devices.].
As per claim 13, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz teaches, a storage device, wherein the buffer manager receives information about the memory area and a start signal of the data preservation operation from the data preservation operation manager [Grosz, Paragraphs 0022- 0023, Both SSDs and managed NAND devices can receive commands from a host in association with memory operations, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory devices and the host, or erase operations to erase data from the memory devices.].
As per claim 14, Grosz and KIM teach all the limitations of claim 1 above, wherein Grosz teaches, a storage device, wherein a size of the buffer memory is smaller than or equal to a size corresponding to a product of a duration of a first period during which the data preservation operation is in progress and a data transmission speed between the host device and the control unit [Grosz, Paragraphs 0123-0124, As the number of dummy memory cells is increased, the reliability in operation of the memory block BLKa may be increased, while the size of the memory block BLKa may be increased. As the number of dummy memory cells is reduced, the size of the memory block BLKa may be reduced, but the reliability in operation of the memory block BLKa may be reduced.].
As per claims 15-18, claims 15-18 are rejected in accordance to the same rational and reasoning as the above claims 1,10-11 and 14, wherein claims 15-18 are the device claims for the device of claims 1,10-11 and 14.
As per claims 19-20, claims 19-20 are rejected in accordance to the same rational and reasoning as the above claims 1 and 2, wherein claims 19-20 are the apparatus claims for the device of claims 1 and 2.
Conclusion
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
References Considered Pertinent but not relied upon
Zhou et al. (US Patent Application Pub. No: 20230409198 A1) teaches a computer device with a memory sharing control device is deployed between a processor and a memory pool, and the processor accesses the memory pool via the memory sharing control device. Zhou discloses different processing units, such as processors or cores in processors, access one memory in the memory pool in different time periods, so that the memory is shared by a plurality of processing units, and utilization of memory resources is improved.
Li et al. (US Patent Application Pub. No: 20230058232 A1) teaches a die command from a requestor is received; and a die command into a die command queue is stored. Li discloses a die command from the die command queue into a plurality of partition commands is partitioned. Li suggests the plurality of partition commands into one of a first plurality of partition command queues or a second plurality of partition command queues is mapped. Li further discloses the partition command of the first plurality of partition command queues or the second plurality of partition command queues is issued to a command processor to be applied to the one or more memory devices.
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/GETENTE A YIMER/Primary Examiner, Art Unit 2181
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